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    Fin-based photodetector structure
    261.
    发明授权
    Fin-based photodetector structure 有权

    公开(公告)号：US11177404B2

    公开(公告)日：2021-11-16

    申请号：US16740719

    申请日：2020-01-13

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Yusheng Bian ,  Steven Shank

    IPC: H01L31/0352 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/028 ,  H01L31/103

    Abstract: A photodetector disclosed herein includes an N-doped waveguide structure defined in a semiconductor material, wherein the N-doped waveguide structure comprises a plurality of first fins. Each adjacent pair of the plurality of first fins is separated by a trench formed in the semiconductor material. The photodetector also includes a detector structure positioned on the N-doped waveguide structure, wherein a portion of the detector structure is positioned laterally between the plurality of first fins. The detector structure comprises a single crystal semiconductor material. The photodetector also includes a first diffusion region that extends from the bottom surface of the trench into the semiconductor material, wherein the first diffusion region comprises atoms of the single crystal semiconductor material of the detector structure.

    High-voltage diode finFET platform designs
    264.
    发明授权
    High-voltage diode finFET platform designs 有权

    公开(公告)号：US11164978B2

    公开(公告)日：2021-11-02

    申请号：US16774482

    申请日：2020-01-28

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Jagar Singh ,  Sudarshan Narayanan

    IPC: H01L29/861 ,  H01L27/08 ,  H01L29/06 ,  H01L29/08

    Abstract: A device includes a substrate having a top surface and a bottom surface. A first doping well having a first part and a second part is located in the substrate. An undoped moat is in the substrate between the first doping well and a second doping well. A diode includes an anode with an increased first doping concentration region in the first doping well and a cathode with an increased second doping concentration region in the second doping well. An isolation region is in the first doping well having a first portion proximate the top surface and a second portion distal to the top surface. A gap made of an undoped region is in the first doping well between the first part and the second part. The gap is located between the distal portion of the isolation region and the bottom surface of the substrate.

    Structure with polycrystalline isolation region below polycrystalline fill shape(s) and selective active device(s), and related method
    268.
    发明授权
    Structure with polycrystalline isolation region below polycrystalline fill shape(s) and selective active device(s), and related method 有权

    公开(公告)号：US11152394B1

    公开(公告)日：2021-10-19

    申请号：US16992445

    申请日：2020-08-13

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Mark D. Levy ,  Siva P. Adusumilli

    IPC: H01L27/12 ,  H01L21/84 ,  H01L21/763

    Abstract: A structure includes a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer over the semiconductor substrate, and an SOI layer over the buried insulator layer. The structure also includes a first active device and a second active device. At least one polycrystalline active region fill shape is in the SOI layer. A polycrystalline isolation region is in the semiconductor substrate under the buried insulator layer. The polycrystalline isolation region is under the first active device, but not under the second active device. The polycrystalline isolation region extends to different depths into the semiconductor substrate. The first and second active devices may include monocrystalline active regions, and a third polycrystalline active region may also be in the SOI layer over the polycrystalline isolation region.

    LOW CLOCK LOAD DYNAMIC DUAL OUTPUT LATCH CIRCUIT
    270.
    发明申请
    LOW CLOCK LOAD DYNAMIC DUAL OUTPUT LATCH CIRCUIT 有权

    公开(公告)号：US20210320650A1

    公开(公告)日：2021-10-14

    申请号：US16847807

    申请日：2020-04-14

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Uttam SAHA ,  Mahbub RASHED

    IPC: H03K3/037 ,  H03K19/20

    Abstract: The present disclosure relates to integrated circuits, and more particularly, to a low clock load dynamic dual output latch circuit and methods of operation. The structure includes: a plurality of dynamic clocked stacks which are configured to receive input data and provide a true logical value and a complement logical value; and a plurality of holding stacks which are configured to provide a hold signal to the dynamic clocked stacks and output the true logical value and the complement logical value in response to the hold signal being activated.

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