公开(公告)号：US20030016571A1

公开(公告)日：2003-01-23

申请号：US10176386

申请日：2002-06-20

Applicant: STMICROELECTRONICS S.A.

Inventor： Paul Ferreira ,  Philippe Coronel

IPC: G11C007/00

CPC classification number: H01L21/823892 ,  H01L21/033 ,  H01L21/266 ,  H01L21/823807

Abstract: The invention relates to a process for treating a portion of the surface of a substrate according to a first and second surface treatments which are different from each other and are intended respectively for a first group of regions and for a second group of regions of the surface portion, the two groups of regions being mutually complementary with respect to the surface portion, the process making it possible to use only a single operation of positioning a mask which differentiates the regions of the first and second groups of regions, using the same protective materials for the regions of each group of regions against the effects of the treatment intended for the regions of the other group of regions. Application to the fabrication of semiconductor products.

Abstract translation: 本发明涉及一种根据彼此不同的第一和第二表面处理来处理基材表面的一部分的方法，分别用于第一组区域和第二组表面区域 部分，两组区域相对于表面部分互相互补，该方法使得仅使用仅使用相同保护材料来区分第一和第二组区域的掩模的单一定位操作 对于每个地区的区域，针对其他地区区域的治疗效果。 适用于制造半导体产品。

公开(公告)号：US20030006431A1

公开(公告)日：2003-01-09

申请号：US10174490

申请日：2002-06-18

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Alexandre Villaret

IPC: H01L031/072

CPC classification number: H01L29/42336 ,  H01L29/788

Abstract: An integrated memory location structure includes an isolated semiconductor layer between the source region and the drain region of a transistor, and between the channel region and the control gate of the transistor. The isolated semiconductor layer includes two potential well zones separated by a potential barrier zone under the control gate of the transistor. A write circuit biases the memory location structure to confine charge carriers selectively in one of the two potential well zones. A read circuit biases the memory location structure to measure the drain current of the transistor and determine therefrom the stored logic state imposed by the position of the charges in one of the potential well zones.

Abstract translation: 集成存储器位置结构包括在晶体管的源极区域和漏极区域之间以及沟道区域和晶体管的控制栅极之间的隔离半导体层。 隔离半导体层包括由晶体管的控制栅极下方的势垒区隔开的两个势阱区。 写入电路偏置存储器位置结构以将电荷载流子选择性地限制在两个势阱区域中的一个中。 读取电路偏置存储器位置结构以测量晶体管的漏极电流，并从其中确定由电荷在一个潜在阱区中施加的存储的逻辑状态。

公开(公告)号：US20020196072A1

公开(公告)日：2002-12-26

申请号：US10164839

申请日：2002-06-06

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G05F001/10

CPC classification number: G05F3/30 ,  G05F3/205 ,  G05F3/262

Abstract: A bias device includes a first branch and a second branch. The first branch includes a first bipolar device and a corresponding bias circuit. The second branch includes a second bipolar device and a corresponding bias circuit. A self-bias circuit is connected to the first and second branches. A first current generator injects a first auxiliary current into the first bipolar device. A second current generator injects a second current into the second bipolar device that is equal or proportional to the first auxiliary current. The bias device stabilizes the operating point of a circuit.

Abstract translation: 偏置装置包括第一分支和第二分支。 第一分支包括第一双极器件和相应的偏置电路。 第二分支包括第二双极器件和相应的偏置电路。 自偏置电路连接到第一和第二分支。 第一电流发生器将第一辅助电流注入第一双极器件。 第二电流发生器将与第一辅助电流相等或成比例的第二电流注入第二双极器件。 偏置装置稳定电路的工作点。

公开(公告)号：US20020185657A1

公开(公告)日：2002-12-12

申请号：US10097651

申请日：2002-03-13

Applicant: STMICROELECTRONICS S.A.

Inventor： Alain Chantre ,  Helene Baudry ,  Didier Dutartre

IPC: H01L031/0328

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.

Abstract translation: 晶体管和双晶硅异质结基极型双极晶体管的制造方法，其中具有SiGe异质结的半导体层通过非选择性外延在衬底的有源区和围绕有源区的绝缘区形成。 在有源区域的一部分上方的半导体层上形成至少一个阻挡层。 在半导体层和停止层的一部分上形成多晶硅层和上绝缘层，留下发射器窗口。 发射极区域通过在发射极窗中外延形成，部分地搁置在上绝缘层上并与半导体层接触。

公开(公告)号：US20020180487A1

公开(公告)日：2002-12-05

申请号：US10115869

申请日：2002-04-03

Applicant: STMicroelectronics S.A.

Inventor： Ahmed Kari ,  Christophe Moreaux

IPC: H03K019/00

CPC classification number: G06K7/10346 ,  G06K7/10019 ,  G06K19/0723 ,  G07C9/00111

Abstract: An integrated circuit having an identification code of M bits includes a communication interface circuit for receiving a selective identification request and a selection code, and a processing circuit connected thereto. The processing circuit includes a logic comparator having a first input for receiving the selection code and a second input for receiving the identification code, and an output for delivering an equal signal if the selection and identification codes are equal. A shift register has an output coupled to the first input of the logic comparator. A serial memory stores the identification code, and has a serial output coupled to the second input of the logic comparator and to a serial input of the shift register. A controller is connected to the shift register and to the serial memory for loading the selection code into the shift register, and for applying M shift pulses to the shift register and M read pulses to the serial memory. An inhibiting circuit inhibits the logic comparator when N shift and read pulses have been applied to the shift register and to the serial memory.

Abstract translation: 具有M位识别码的集成电路包括用于接收选择性识别请求和选择码的通信接口电路以及与其连接的处理电路。 处理电路包括具有用于接收选择码的第一输入和用于接收识别码的第二输入的逻辑比较器，以及如果选择和识别码相等则输出相等信号的输出。 移位寄存器具有耦合到逻辑比较器的第一输入的输出。 串行存储器存储识别码，并且具有耦合到逻辑比较器的第二输入端的串行输出和移位寄存器的串行输入。 控制器连接到移位寄存器和串行存储器，用于将选择代码加载到移位寄存器中，并且将M移位脉冲施加到移位寄存器，并将M个读取脉冲施加到串行存储器。 当N移位和读取脉冲已经被施加到移位寄存器和串行存储器时，抑制电路禁止逻辑比较器。

公开(公告)号：US20020177265A1

公开(公告)日：2002-11-28

申请号：US10114329

申请日：2002-04-02

Applicant: STMICROELECTRONICS S.A.

Inventor： Thomas Skotnicki ,  Emmanuel Josse

IPC: H01L021/8238

CPC classification number: H01L29/66666 ,  H01L21/2807 ,  H01L21/2815 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/7827

Abstract: The vertical transistor includes, on a semiconductor substrate, a vertical pillar 5 having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layer 7 situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first region 800 resting on the gate dielectric layer 7 and a second region 90 facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities 14S, 14D.

Abstract translation: 垂直晶体管在半导体衬底上包括在顶部具有源极和漏极区中的一个的垂直柱5，源极和漏极区中的另一个位于柱的外围的衬底中，栅极介电层 7位于柱的侧面和基板的顶表面上，以及位于栅极介电层上的半导体栅极。 栅极包括具有搁置在栅极电介质层7上的第一区域800的半导体块和面向源极和漏极区域的至少部分的第二区域90，并且通过电介质腔14S，14D与那些源极和漏极区域分离。

公开(公告)号：US20020176289A1

公开(公告)日：2002-11-28

申请号：US10117446

申请日：2002-04-03

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Cyrille Dray ,  Daniel Caspar

IPC: G11C007/00

CPC classification number: G11C16/0416 ,  G11C16/0408

Abstract: A FAMOS memory cell is electrically erased. The FAMOS memory cell may be electrically erased by applying to the substrate a voltage having a value at least 4 volts higher than the lower of a voltage applied to the source and a voltage applied to the drain. The voltage applied to the substrate is also less than a predetermined limit above which the memory cell is destroyed.

Abstract translation: FAMOS存储单元被电擦除。 可以通过向基板施加比施加到源极的电压的低至少4伏的电压和施加到漏极的电压来电存储FAMOS存储单元。 施加到基板的电压也小于预定的限制，高于该预定限度，存储单元被破坏。

公开(公告)号：US20020167973A1

公开(公告)日：2002-11-14

申请号：US10141621

申请日：2002-05-08

Applicant: STMicroelectronics S.A.

Inventor： Thomas Alofs

IPC: H04J003/02

CPC classification number: H03K17/005 ,  H03K3/037

Abstract: A multiplexed flip-flop electronic device includes a decoder logic circuit for providing a first switching signal, and a control circuit for receiving a clock signal and for providing a gated clock signal forming a second switching signal. The electronic device further includes a multiplexing circuit having N inputs and an output, and a flip flop circuit. The flip-flop circuit includes a first switching stage connected between the N inputs and the output of the multiplexing circuit, and includes N switches being individually controlled by the first switching signal. A first buffer stage is connected to the output of the multiplexing circuit, and a second switching stage is connected to an output of the first buffer stage. The second switching stage is controlled by the second switching signal. A second buffer stage is connected to an output of the second switching stage.

Abstract translation: 多路触发器电子设备包括用于提供第一切换信号的解码器逻辑电路和用于接收时钟信号并提供形成第二切换信号的门控时钟信号的控制电路。 电子设备还包括具有N个输入和输出的多路复用电路和一个触发器电路。 触发器电路包括连接在N个输入和多路复用电路的输出之间的第一开关级，并且包括由第一开关信号单独控制的N个开关。 第一缓冲级连接到多路复用电路的输出端，第二开关级与第一缓冲级的输出相连。 第二开关级由第二开关信号控制。 第二缓冲级连接到第二开关级的输出端。

公开(公告)号：US20020163364A1

公开(公告)日：2002-11-07

申请号：US10113859

申请日：2002-04-01

Applicant: STMicroelectronics S.A.

Inventor： Sylvain Majcherczak ,  Guy Mabboux

IPC: H03K005/153

CPC classification number: H03K17/302 ,  H03K17/223 ,  H03K19/0016 ,  H03K19/007

Abstract: In an integrated circuit, a detection device detects a drop in the supply voltage of the core of the integrated circuit or an excessively slow build-up of this voltage with respect to a supply voltage of the input/output interface circuits of the integrated circuit. Outputs of the interface circuits are set to a high impedance state by the detection device to minimize their power consumption.

Abstract translation: 在集成电路中，检测装置检测集成电路的磁芯的电源电压的下降或相对于集成电路的输入/输出接口电路的电源电压过度缓慢的累积。 通过检测装置将接口电路的输出设置为高阻抗状态，以最小化其功耗。

公开(公告)号：US20020159308A1

公开(公告)日：2002-10-31

申请号：US10062271

申请日：2002-02-01

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Leila Sedjai Aitouarab

IPC: G11C007/00

CPC classification number: G11C16/3431 ,  G11C16/3418

Abstract: Reference cells are refreshed in a non-volatile memory that includes a plurality of memory cells. A selected reference cell and a non-used memory cell are read simultaneously, and a signal read from the reference cell is compared to a signal read from the non-used memory cell. A refresh signal for refreshing the reference cell is supplied when the signal read therefrom is less than the signal read from the non-used memory cell.

Abstract translation: 参考单元在包括多个存储单元的非易失性存储器中刷新。 同时读取选择的参考单元和未使用的存储单元，并将从参考单元读取的信号与从未使用的存储单元读取的信号进行比较。 当从其读取的信号小于从未使用的存储单元读取的信号时，提供刷新参考单元的刷新信号。