-
公开(公告)号：US09994441B2
公开(公告)日：2018-06-12
申请号：US15339149
申请日：2016-10-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Simon Joshua Jacobs
CPC classification number: B81C1/00317 , B81B3/0083 , B81B7/0067 , B81B2201/042 , B81B2207/015 , B81C1/00047 , B81C1/00119 , B81C1/00261 , B81C1/00269 , B81C1/00595 , B81C2201/014 , B81C2203/0109 , B81C2203/0118 , B81C2203/0127 , B81C2203/0145 , B81C2203/0735 , B81C2203/0771 , G02B1/115 , G02B26/0833
Abstract: For an optical electronic device and method that forms cavities through an interposer wafer after bonding the interposer wafer to a window wafer, the cavities are etched into the bonded interposer/window wafer pair using the anti-reflective coating of the window wafer as an etch stop. After formation of the cavities, the bonded interposer/window wafer pair is bonded peripherally of die areas to the MEMS device wafer, with die area micromechanical elements sealed within respectively corresponding ones of the cavities.
-
272.发明授权公开(公告)号：US09833780B2
公开(公告)日：2017-12-05
申请号：US14830059
申请日：2015-08-19
Applicant: University of South Carolina
Inventor： Chen Li , Fanhao Yang , Xianming Dai , Yan Tong
CPC classification number: B01L3/502707 , B01J19/0093 , B01J2219/00783 , B01J2219/00828 , B01J2219/00835 , B01J2219/00846 , B01J2219/0086 , B01L3/502715 , B01L2200/12 , B01L2300/0858 , B01L2300/12 , B81B1/00 , B81B7/0087 , B81B2201/058 , B81B2203/033 , B81B2203/0361 , B81C1/00031 , B81C1/00111 , B81C1/00119 , B81C1/00206 , B81C2201/014 , Y10T137/0318 , Y10T428/24496
Abstract: Microfluidic devices having superhydrophilic bi-porous interfaces are provided, along with their methods of formation. The device can include a substrate defining a microchannel formed between a pair of side walls and a bottom surface and a plurality of nanowires extending from each of the side walls and the bottom surface. For example, the nanowires can be silicon nanowires (e.g., pure silicon, silicon oxide, silicon carbide, etc., or mixtures thereof).
-
公开(公告)号：US20170341934A1
公开(公告)日：2017-11-30
申请号：US15680996
申请日：2017-08-18
Applicant: Texas Instruments Incorporated
Inventor： Lee Alan Stringer , Mona Eissa , Byron J.R. Shulver , Sopa Chevacharoenkul , Mark R. Kimmich , Sudtida Lavangkul , Mark L. Jenson
CPC classification number: B81C1/00825 , B81C1/00365 , B81C2201/0138 , B81C2201/014 , G01R33/0047 , G01R33/0052 , G01R33/04
Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.
-
公开(公告)号：US09790088B2
公开(公告)日：2017-10-17
申请号：US14993105
申请日：2016-01-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Meng-Jia Lin , Yung-Hsiao Lee , Weng-Yi Chen , Shih-Wei Li , Chung-Hsien Liu
CPC classification number: B81C1/00246 , B81B7/008 , B81B2201/0235 , B81B2201/0285 , B81B2203/0315 , B81B2207/012 , B81B2207/015 , B81C1/00571 , B81C2201/0132 , B81C2201/014
Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
-
275.发明申请公开(公告)号：US20170274658A1
公开(公告)日：2017-09-28
申请号：US15464903
申请日：2017-03-21
Applicant: CANON KABUSHIKI KAISHA
Inventor： Atsunori Terasaki
CPC classification number: B41J2/1601 , B41J2/0458 , B41J2/14032 , B41J2/1603 , B41J2/162 , B41J2/1628 , B41J2/1629 , B41J2/1631 , B41J2/164 , B41J2002/14467 , B41J2202/22 , B81B2201/052 , B81B2203/0353 , B81C1/00206 , B81C1/00619 , B81C2201/0132 , B81C2201/014
Abstract: A method for processing a silicon substrate includes forming a structure having a bottom surface and a depth of 200 μm or more or 300 μm or more from a first surface of a silicon substrate, forming a protective film on an inner wall of the structure, and performing plasma etching so as to selectively remove the protective film disposed on the bottom surface of the structure with respect to the protective film disposed on the substantially perpendicular side wall of the structure, wherein the plasma etching is performed under the condition in which plasma with a sheath length at least 10 times the depth when the depth is 200 μm or more, or at least 5 time the depth when the depth is 300 μm or more, is generated and a mean free path of ions generated in the plasma is longer than the sheath length.
-
Patent Agency Ranking
公开(公告)号：US20170267521A1
公开(公告)日：2017-09-21
申请号：US15072852
申请日：2016-03-17
Applicant: Texas Instruments Incorporated
Inventor： Lee Alan Stringer , Mona Eissa , Byron J.R. Shulver , Sopa Chevacharoenkul , Mark R. Kimmich , Sudtida Lavangkul , Mark L. Jenson
CPC classification number: B81C1/00825 , B81C1/00365 , B81C2201/0138 , B81C2201/014 , G01R33/0047 , G01R33/0052 , G01R33/04
Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.
-
公开(公告)号：US09758373B2
公开(公告)日：2017-09-12
申请号：US14262437
申请日：2014-04-25
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano Losa , Raffaella Pezzuto , Roberto Campedelli , Matteo Perletti , Luigi Esposito , Mikel Azpeitia Urquia
CPC classification number: H01L21/02178 , B81B7/0032 , B81B2201/0235 , B81B2201/0242 , B81C1/00595 , B81C1/00801 , B81C2201/014 , B81C2201/053 , H01L21/0228
Abstract: A method for manufacturing a protective layer for protecting an intermediate structural layer against etching with hydrofluoric acid, the intermediate structural layer being made of a material that can be etched or damaged by hydrofluoric acid, the method comprising the steps of: forming a first layer of aluminum oxide, by atomic layer deposition, on the intermediate structural layer; performing a thermal crystallization process on the first layer of aluminum oxide, forming a first intermediate protective layer; forming a second layer of aluminum oxide, by atomic layer deposition, above the first intermediate protective layer; and performing a thermal crystallization process on the second layer of aluminum oxide, forming a second intermediate protective layer and thereby completing the formation of the protective layer. The method for forming the protective layer can be used, for example, during the manufacturing steps of an inertial sensor such as a gyroscope or an accelerometer.
-
公开(公告)号：US09731964B2
公开(公告)日：2017-08-15
申请号：US15171002
申请日：2016-06-02
Applicant: Nivarox-FAR S.A.
Inventor： Alex Gandelhman , Andre Pin
CPC classification number: B81C1/00619 , B81B2201/035 , B81B2203/0384 , B81C1/00103 , B81C2201/0112 , B81C2201/0132 , B81C2201/0138 , B81C2201/014 , B81C2201/0188 , B81C2201/0198 , G04B13/02 , G04B13/026 , G04B13/027 , G04D99/00
Abstract: The invention relates to a silicon-based component with at least one reduced contact surface which, formed from a method combining at least one oblique side wall etching step with a “Bosch” etch of vertical side walls, improves, in particular, the tribology of components formed by micromachining a silicon-based wafer.
-
279.发明授权公开(公告)号：US09682858B2
公开(公告)日：2017-06-20
申请号：US14943315
申请日：2015-11-17
Applicant: Seiko Epson Corporation
Inventor： Nobuyuki Tanaka
IPC: B81C1/00 , H01L21/762 , G01L9/00 , G01L5/06
CPC classification number: B81C1/00801 , B81C1/00158 , B81C1/00293 , B81C2201/014 , B81C2203/0136 , G01L5/06 , G01L9/0042 , G01L9/0045 , G01L9/0054 , G01L9/0073 , G01L9/008 , H01L21/76264 , H01L21/76283
Abstract: An physical quantity sensor includes a substrate, a piezoelectric resistive element that is disposed on one surface side of the substrate, a wall portion that is disposed on the one surface side of the substrate so as to surround the piezoelectric resistive element in a plan view of the substrate, and a ceiling portion that is disposed on an opposite side to the substrate with respect to the wall portion and forms a cavity along with the wall portion, in which the wall portion includes an insulating layer, and wiring layers that surround the insulating layer together and have higher resistance to an etchant which can etch the insulating layer than resistance of the insulating layer.
-
公开(公告)号：US20170166441A1
公开(公告)日：2017-06-15
申请号：US14993105
申请日：2016-01-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Meng-Jia Lin , Yung-Hsiao Lee , Weng-Yi Chen , Shih-Wei Li , Chung-Hsien Liu
CPC classification number: B81C1/00246 , B81B7/008 , B81B2201/0235 , B81B2201/0285 , B81B2203/0315 , B81B2207/012 , B81B2207/015 , B81C1/00571 , B81C2201/0132 , B81C2201/014
Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
-
-
-
-
-
-
-
-
-
Search Results
337
records
(took 0.018 seconds)
