公开(公告)号：US08258810B2

公开(公告)日：2012-09-04

申请号：US12894252

申请日：2010-09-30

Applicant: Zvi Or-Bach ,  Ze'ev Wurman

Inventor： Zvi Or-Bach ,  Ze'ev Wurman

IPC: H03K19/177 ,  H01L23/02

CPC classification number: H03K19/17728 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/11803 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06544 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3011 ,  H03K19/17796 ,  H01L2924/00

Abstract: A semiconductor device includes a first transistor layer and a second transistor layer overlaying the first transistor layer, wherein said first transistor layer comprises a plurality of flip-flops each having a selectively coupleable additional input generated by said second transistor layer.

Abstract translation: 半导体器件包括覆盖第一晶体管层的第一晶体管层和第二晶体管层，其中所述第一晶体管层包括多个触发器，每个触发器具有由所述第二晶体管层产生的选择性可耦合的附加输入。

公开(公告)号：US08115511B2

公开(公告)日：2012-02-14

申请号：US12797493

申请日：2010-06-09

Applicant: Zvi Or-Bach

Inventor： Zvi Or-Bach

IPC: G06F7/38 ,  H01L25/00

CPC classification number: H03K19/17748 ,  H01L2924/0002 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17796 ,  H01L2924/00

Abstract: A configurable integrated circuit (IC) system comprising: a first die comprising input/output cells; and a configurable logic second die connected by a first plurality of through-silicon-vias (TSVs) to the first die.

Abstract translation: 一种可配置集成电路（IC）系统，包括：包括输入/​​输出单元的第一管芯; 以及由第一多个穿硅通孔（TSV）连接到第一管芯的可配置逻辑第二管芯。

公开(公告)号：US20120028436A1

公开(公告)日：2012-02-02

申请号：US13246391

申请日：2011-09-27

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L21/027

CPC classification number: G11C17/14 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/17764 ,  H03K19/17796 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks and at least one of the second alignment marks.

Abstract translation: 一种制造半导体晶片的方法，所述方法包括：提供包括半导体衬底，金属层和第一对准标记的基底晶片; 在所述金属层的顶部上转移单晶层，其中所述单晶层包括第二对准标记; 以及使用所述第一对准标记和所述第二对准标记中的至少一个来执行光刻。

公开(公告)号：US08058137B1

公开(公告)日：2011-11-15

申请号：US13083802

申请日：2011-04-11

Applicant: Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/76

CPC classification number: H01L27/088 ,  G11C17/14 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8226 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/177 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks in a first direction and at least one of the second alignment marks in a second direction.

Abstract translation: 一种制造半导体晶片的方法，所述方法包括：提供包括半导体衬底，金属层和第一对准标记的基底晶片; 在所述金属层的顶部上转移单晶层，其中所述单晶层包括第二对准标记; 以及使用第一方向上的第一对准标记中的至少一个和第二对准标记中的至少一个沿第二方向进行光刻。

公开(公告)号：US07986042B2

公开(公告)日：2011-07-26

申请号：US12849272

申请日：2010-08-03

Applicant: Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar

IPC: H01L23/58 ,  H01L23/528 ,  H01L21/98

CPC classification number: H01L27/08 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/80001

Abstract: A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layers; wherein the second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands wherein each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

Abstract translation: 一种半导体器件，包括：包含第一晶体管，第一对准标记和覆盖在第一单晶硅层上的至少一个金属层的第一单晶硅层，其中所述至少一个金属层比其它材料包括铜或铝; 以及覆盖所述至少一个金属层的第二单晶硅层; 其中所述第二单晶硅层包括以基本上平行的带布置的多个第二晶体管，其中所述多个所述带中的每一个包括沿重复图案的轴的所述第二晶体管的一部分。

公开(公告)号：US20250132187A1

公开(公告)日：2025-04-24

申请号：US18991504

申请日：2024-12-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/25 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H10D10/01 ,  H10D30/01 ,  H10D30/60 ,  H10D30/68 ,  H10D30/69 ,  H10D64/01 ,  H10D64/27 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D84/90 ,  H10D86/00 ,  H10D86/01 ,  H10D86/40 ,  H10D86/60 ,  H10D88/00 ,  H10D89/10

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors each of which includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors and overlaying the second metal layer, each of first memory cells include at least one second transistor; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors and overlaying the third level, each of second memory cells include at least one fourth transistor, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one of the second transistors includes a hafnium oxide gate dielectric.

公开(公告)号：US20250098325A1

公开(公告)日：2025-03-20

申请号：US18959033

申请日：2024-11-25

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  G03F9/00 ,  H01L21/268 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/732 ,  H01L29/786 ,  H01L29/808 ,  H01L29/812 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20

Abstract: A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.

公开(公告)号：US12199093B2

公开(公告)日：2025-01-14

申请号：US18668218

申请日：2024-05-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  G03F9/00 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  H01L27/02 ,  H01L27/092 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/732 ,  H01L29/786 ,  H01L29/808 ,  H01L29/812 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20 ,  H01L21/268 ,  H01L23/00 ,  H01L27/088

Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, disposed over the third metal layer; a third level including a plurality of third transistors, disposed over the second level; a via disposed through the second and third levels; a fourth metal layer disposed over the third level; a fifth metal layer disposed over the fourth metal layer; and a fourth level including a second single crystal silicon layer and is disposed over the fifth metal layer, where each of the plurality of second transistors includes a metal gate, and the via has a diameter of less than 450 nm.

公开(公告)号：US20240395592A1

公开(公告)日：2024-11-28

申请号：US17942109

申请日：2022-09-09

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/20 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

Abstract: A method for producing a 3D memory device including: providing a first level including a first single-crystal layer and control circuits, where the first level includes at least two interconnecting metal layers; forming at least one second level disposed above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; each of first memory cells include one first transistor and each of second memory cells include one second transistor, where first memory cells and second memory cells are a NAND nonvolatile type memory, and at least one of the second transistors include a metal gate.

公开(公告)号：US20240379502A1

公开(公告)日：2024-11-14

申请号：US18778977

申请日：2024-07-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/48 ,  H01L21/74 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L27/118 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L29/808 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H10B63/00

Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.