公开(公告)号：US20190067474A1

公开(公告)日：2019-02-28

申请号：US15686257

申请日：2017-08-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu WONG ,  Hui ZANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L29/165 ,  H01L29/10

Abstract: A polysilicon layer is deposited over the top surface of the source/drain region of a semiconductor fin in a vertical fin field effect transistor and recrystallized prior to the formation of an epitaxial source/drain region over the source/drain region. The recrystallized silicon material increases the area for deposition of the source/drain region, increasing the available contact area of the source/drain region and correspondingly decreasing the contact resistance thereto. Prior to recrystallization, the polysilicon layer may be made amorphous to improve the quality of the crystalline material for epitaxial growth.

公开(公告)号：US20190067210A1

公开(公告)日：2019-02-28

申请号：US15690398

申请日：2017-08-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas A. Polomoff ,  Vincent J. McGahay

IPC: H01L23/00 ,  H01L23/58

Abstract: A seal ring structure of an integrated circuit including a first discontinuous seal wall circumscribing a first portion of the integrated circuit, the first seal wall forming a first pattern on a substrate, and a second discontinuous seal wall circumscribing a second portion of the integrated circuit, the second seal wall forming a second pattern on the substrate and the second portion being at least partially offset from the first portion, wherein the first pattern of the first seal wall interlocks with the second pattern of the second seal wall such that the patterns are interweaved without intersecting, wherein a space is formed between the seal walls, the space creating a non-linear path to the integrated circuit, and wherein the seal ring structure fully circumscribes the integrated circuit. A method of forming such a seal ring structure is also disclosed.

公开(公告)号：US20190067191A1

公开(公告)日：2019-02-28

申请号：US15686230

申请日：2017-08-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu Wong ,  Jagar Singh

IPC: H01L23/525 ,  H01L23/528 ,  H01L21/762 ,  H01L29/161

CPC classification number: H01L23/5256 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/528 ,  H01L29/161

Abstract: Methods of forming a hybrid electrically programmable fuse (e-fuse) structure and the hybrid e-fuse structure are disclosed. In various embodiments, the e-fuse structure includes: a substrate; an insulator layer over the substrate; a pair of contact regions overlying the insulator layer; and a silicide channel overlying the insulator layer and connecting the pair of contact regions, the silicide channel having a first portion including silicide silicon and a second portion coupled with the first portion and on a common level with the first portion, the second portion including silicide silicon germanium (SiGe) or silicide silicon phosphorous (SiP).

公开(公告)号：US20190067098A1

公开(公告)日：2019-02-28

申请号：US15687591

申请日：2017-08-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Aditya Kumar ,  Shiv Kumar Mishra ,  Jean-Baptiste Jacques Laloë ,  Wen Zhi Gao

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L23/532 ,  H01L23/535

Abstract: Methods of forming a contact for a semiconductor device with double barrier layer sets, and a device so formed are disclosed. Methods may include: depositing a first metal layer contacting a semiconductor substrate in a contact opening; depositing a first nitride barrier layer on the first metal layer; and annealing after depositing the first nitride barrier layer to form silicide region in a junction area underlying the contact opening with the first metal layer and the semiconductor substrate. After the annealing, a second metal layer may be deposited, followed by a second nitride barrier layer. A conductor is formed in a remaining portion of the contact opening. The double barrier layer sets prevent the formation of volcano defects and also advantageously reduce contact resistance.

公开(公告)号：US10217900B2

公开(公告)日：2019-02-26

申请号：US15643061

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deepak K. Nayak ,  Srinivasa R. Banna ,  Ajey P. Jacob

IPC: H01L33/12 ,  H01L33/00 ,  H01L33/06 ,  H01L33/32 ,  H01L33/22

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diode (LED) structures and methods of manufacture. The method includes: forming a buffer layer on a substrate, the buffer layer having at least a lattice mismatch with the substrate; and relaxing the buffer layer by pixelating the buffer layer into discrete islands, prior to formation of a quantum well.

公开(公告)号：US20190056671A1

公开(公告)日：2019-02-21

申请号：US15681007

申请日：2017-08-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  John Zhang ,  Shao Beng Law ,  Guoxiang Ning ,  Xunyuan Zhang ,  Ruilong Xie

IPC: G03F7/20 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  C23C14/22 ,  C23C16/455

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay mark structures and methods of manufacture. The method includes: forming an overlay mark within a layer of a stack of layers; increasing a density of an upper layer of the stack of layers, above the layer, the increased density protecting the overlay mark; and polishing the upper layer or one or more layers above the upper layer of the stack of layers.

公开(公告)号：US10211206B1

公开(公告)日：2019-02-19

申请号：US15800905

申请日：2017-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238

Abstract: Methods of connecting a read driver transistor to a PD and PU inverter of a two-port vertical SRAM via a shared GAA or a vertical cross-couple contact between a GAA of the read driver transistor and the bottom source/drain region of the PD and PU inverter and the resulting devices are provided. Embodiments include forming a first PD transistor, a first PU transistor, a second PU transistor, and a second PD transistor over a substrate; forming a first PG transistor and a second PG transistor over the substrate; forming a read transistor and a read driver transistor laterally separated in the first direction over the substrate, the read transistor and the read driver transistor adjacent to the second PG transistor and the first PD transistor, respectively; and connecting the read driver transistor, the first PD transistor, and the first PU transistor.

公开(公告)号：US10211094B2

公开(公告)日：2019-02-19

申请号：US15641861

申请日：2017-07-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/485 ,  H01L23/532 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

公开(公告)号：US10211090B2

公开(公告)日：2019-02-19

申请号：US15291561

申请日：2016-10-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L29/732 ,  H01L29/737 ,  H01L23/482 ,  H01L23/31

Abstract: Disclosed are embodiments of a transistor, which incorporates an airgap for low base-emitter capacitance (Cbe). Each embodiment of the transistor has a monocrystalline base and, within the monocrystalline base, an intrinsic base region and an extrinsic base region positioned laterally adjacent to the intrinsic base region, wherein the intrinsic and extrinsic base regions have co-planar top surfaces. An essentially T-shaped emitter in cross-section has a lower emitter region on the intrinsic base region and an upper emitter region above the lower emitter region. Each embodiment of the transistor further has an airgap, which is positioned laterally adjacent to the lower emitter region so as to be between the extrinsic base region and the upper emitter region. Thus, the entire airgap is above the co-planar top surfaces of the intrinsic base region and the extrinsic base region. Also disclosed herein are methods of forming the transistor embodiments.

公开(公告)号：US20190051659A1

公开(公告)日：2019-02-14

申请号：US15673548

申请日：2017-08-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Tenko Yamashita ,  Kangguo Cheng

IPC: H01L27/11556 ,  H01L27/11526

Abstract: The disclosure is directed to an integrated circuit structure and method of forming the same. The integrated circuit structure may include: a first device region including: a floating gate structure substantially surrounding a first fin that is over a substrate; a first bottom source/drain within the substrate, and beneath the first fin and the floating gate structure; a first top source/drain over the first fin and the floating gate structure; a first spacer substantially surrounding the first top source/drain and disposed over the floating gate structure; and a gate structure substantially surrounding and insulated from the floating gate structure, the gate structure being disposed over the substrate and having a height greater than a height of the floating gate.