公开(公告)号：US10298186B2

公开(公告)日：2019-05-21

申请号：US14931102

申请日：2015-11-03

Applicant: RF Micro Devices, Inc.

Inventor： Dirk Robert Walter Leipold ,  George Maxim ,  Baker Scott

IPC: H04W4/00 ,  H03F3/193 ,  H03F1/26 ,  H04B1/10 ,  H04B7/08 ,  H04W72/04 ,  H03F1/02 ,  H03F1/22

Abstract: A carrier aggregation front-end module with a receive sub-module for receiving signals from a plurality of transmit modules. The module comprises a first receive path configured to receive a first set of signals from one or more of a plurality of antennas, wherein the first set of signals comprises at least one desired receive signal and at least one undesired transmit blocker signal from the plurality of transmit modules. The second receive path is configured to receive a second set of signals from one or more of a plurality of antennas comprising at least one desired receive signal and at least one undesired transmit blocker signal from the plurality of transmit modules. The module also comprises at least one shared tunable notch filter configured to reject at least one of the undesired transmit blocker signals for each of the first receive path and the second receive path.

公开(公告)号：US10282269B2

公开(公告)日：2019-05-07

申请号：US14659328

申请日：2015-03-16

Applicant: RF Micro Devices, Inc.

Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala

IPC: G06F11/30 ,  H04L1/16 ,  H04L7/027 ,  H04L1/00 ,  G06F1/10 ,  G06F11/00 ,  G06F13/362 ,  G06F11/22 ,  G06F1/26

Abstract: Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.

公开(公告)号：US10062494B2

公开(公告)日：2018-08-28

申请号：US14929608

申请日：2015-11-02

Applicant: RF Micro Devices, Inc.

Inventor： Dirk Robert Walter Leipold ,  George Maxim ,  Marcus Granger-Jones ,  Baker Scott

IPC: H01F27/28 ,  H01F17/00 ,  H04J1/08 ,  H03H7/46 ,  H03H7/38 ,  H04B1/40

CPC classification number: H01F27/2804 ,  H01F2027/2809 ,  H01L21/0276 ,  H01L28/10 ,  H01P7/06 ,  H01P7/065 ,  H01P7/08 ,  H03H7/38 ,  H03H7/463 ,  H03H9/24 ,  H04B1/40 ,  H04J1/08

Abstract: Embodiments of an apparatus are disclosed that includes a first three dimensional (3D) inductor and a second 3D inductor. The first three dimensional (3D) inductor has a first conductive path shaped as a first two dimensional (2D) lobe laid over a first 3D volume. In addition, the second 3D inductor has a second conductive path, wherein the second 3D inductor is inserted into the first 3D inductor so that the second conductive path at least partially extends through the first 3D volume. Since second 3D inductor is inserted into the first 3D inductor, the 3D inductors may be coupled to one another. Depending on orientation and distances of structures provided by the 3D inductors, the 3D inductors may be weakly or moderately coupled.

公开(公告)号：US10049026B2

公开(公告)日：2018-08-14

申请号：US14659379

申请日：2015-03-16

Applicant: RF Micro Devices, Inc.

Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala

IPC: G06F11/30 ,  G06F1/26 ,  G06F1/10 ,  G06F11/22 ,  G06F11/16 ,  G06F11/10

Abstract: Embodiments of bus interface systems and methods of operating the same are disclosed. In one embodiment, a bus interface system includes a master bus controller and multiple slave bus controllers that are each coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. Each of the slave bus controllers decodes the first set of data pulses along the bus line representing the payload segment and performs an error check. Each slave bus controller is then configured to generate an acknowledgement pulse along the bus line to indicate that the slave bus controller's particular error check was passed. In this manner, the bus interface system can perform a group write bus function and the master bus controller can determine that the multiple slave bus controllers each received an accurate copy of the payload segment.

公开(公告)号：US09973173B2

公开(公告)日：2018-05-15

申请号：US15010829

申请日：2016-01-29

Applicant: RF Micro Devices, Inc.

Inventor： Nadim Khlat ,  Marcus Granger-Jones

IPC: H01P1/10 ,  H01P1/213 ,  H03H19/00 ,  H04B1/00 ,  H04B1/44 ,  H03H7/46

CPC classification number: H03H19/002 ,  H03H7/465 ,  H03H2250/00 ,  H04B1/006

Abstract: This disclosure relates to radio frequency (RF) front end circuitry used to route RF signals. In one embodiment, the RF front end circuitry has a filter circuit and a switch device. The switch device includes a common port, an RF port, and switchable path connected in series between the common port and the RF port. The switch device is configured to present approximately the filter capacitance of the filter circuit at the common port when the switchable path is closed. However, when the switchable path is open, the switch device is configured to present a device capacitance at the common port that is approximately equal to the filter capacitance of the filter circuit. In this manner, if the common port is connected to an antenna, the capacitance seen by the antenna from the common port remains substantially unchanged regardless of which of the switchable path is opened or closed.

公开(公告)号：US09972999B2

公开(公告)日：2018-05-15

申请号：US14819507

申请日：2015-08-06

Applicant: RF Micro Devices, Inc.

Inventor： Nathaniel Peachey

IPC: H02H9/04 ,  H02H3/44

CPC classification number: H02H9/046 ,  H02H3/44

Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. In this regard, an ESD protection circuit is provided to protect an integrated circuit (IC) from an ESD event. In one aspect, an ESD voltage detection circuitry activates an ESD clamping circuitry when an ESD voltage associated with faster voltage rise time is detected between a supply rail and a ground rail. In another aspect, an operation voltage detection circuitry deactivates the ESD clamping circuitry when an operation voltage associated with slower voltage rise time is detected between the supply rail and the ground rail. By differentiating the ESD voltage from the operation voltage based on respective voltage rise times, it is possible to prevent the ESD clamping circuitry from missing the ESD voltage associated with the faster voltage rise time or being falsely activated by the operation voltage associated with the slower voltage rise time.

公开(公告)号：US09972425B2

公开(公告)日：2018-05-15

申请号：US14946028

申请日：2015-11-19

Applicant: RF Micro Devices, Inc.

Inventor： Peter V. Wright ,  Kerry Burger

IPC: H03H11/04 ,  H01C7/00 ,  H04B1/04 ,  H03H7/46 ,  H03K17/0412 ,  H03K17/10 ,  H01C1/01 ,  H03H7/52

CPC classification number: H01C7/006 ,  H01C1/01 ,  H03H7/465 ,  H03H7/52 ,  H03K17/04123 ,  H03K17/102 ,  H04B1/0475

Abstract: A frequency-dependent resistor and circuitry employing the same are provided. In some embodiments, a resistor includes a substrate, an input port, an output port, and a conductive trace on the substrate between the input port and the output port. A resistance between the input port and the output port for a low frequency signal is at least five times lower than the resistance between the input port and the output port for an RF signal and the ratio of the frequencies of the RF signal to the low frequency signal is at least fifty. Circuitry including a transistor adapted to selectively couple the input to the output in response to a control signal provided via a resistor with resistance for a low frequency signal at least five times lower than resistance for an RF signal will have a reduced switching time while still isolating the RF signal.

公开(公告)号：US09966671B2

公开(公告)日：2018-05-08

申请号：US14613105

申请日：2015-02-03

Applicant: RF Micro Devices, Inc.

Inventor： Ali Tombak ,  Marcus Granger-Jones

IPC: H01Q3/24 ,  H01Q21/28 ,  H01Q1/52

CPC classification number: H01Q21/28 ,  H01Q1/523

Abstract: RF circuitry, which includes a first main RF switching circuit and a second main RF switching circuit, is disclosed. The first main RF switching circuit is capable of providing an RF signal path between a first main RF port and a first selected one of a first RF antenna and a second RF antenna. The second main RF switching circuit is capable of providing an RF signal path between a second main RF port and a second selected one of the first RF antenna and the second RF antenna. The first main RF switching circuit includes a first pair of RF switches coupled in series between the first RF antenna and the first main RF port; a second pair of RF switches coupled in series between the second RF antenna and the first main RF port; a first shunt RF switch; and a second shunt RF switch.

公开(公告)号：US09935662B2

公开(公告)日：2018-04-03

申请号：US15131417

申请日：2016-04-18

Applicant: RF Micro Devices, Inc.

Inventor： Nadim Khlat ,  Andrew F. Folkmann

IPC: H04B1/00 ,  H04B1/04 ,  H04L5/14

CPC classification number: H04B1/006 ,  H03F3/24 ,  H04B1/0458 ,  H04B1/0475 ,  H04B2001/0408 ,  H04L5/14

Abstract: A front-end module configured to cancel unwanted transmit spectrum at one or more receivers comprises at least one transmitter having a power amplifier and configured to transmit signals to an antenna. The front-end module also comprises at least one receiver to receive the transmit signals, wherein the at least one receiver receives at least a portion of unwanted transmit spectrum. A directional coupler couples at least a portion of a transmit output signal from the power amplifier to provide a coupled transmit output signal to signal conditioning circuitry associated with the at least one receiver and configured to condition the coupled transmit output signal to generate a conditioned transmit signal to provide to the at least one receiver, wherein the conditioned transmit signal at least partially cancels the unwanted transmit spectrum. The signal conditioning circuitry may adjust the amplitude and phase of the coupled transmit output signal.

公开(公告)号：US09935031B2

公开(公告)日：2018-04-03

申请号：US14885202

申请日：2015-10-16

Applicant: RF Micro Devices, Inc.

Inventor： Dirk Robert Walter Leipold ,  Julio C. Costa ,  Baker Scott ,  George Maxim

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/304 ,  H01L21/02 ,  H01L21/683 ,  H01L23/373 ,  H01L23/00 ,  H05K1/02 ,  H05K1/18 ,  H01Q1/50 ,  H01L23/36 ,  H01L21/56 ,  H01L23/20 ,  H01L23/367 ,  H01L21/306 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/315 ,  H01L21/02266 ,  H01L21/02282 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/20 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/3737 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/562 ,  H01L24/17 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/0002 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01Q1/50 ,  H05K1/0203 ,  H05K1/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.