公开(公告)号：US5422587A

公开(公告)日：1995-06-06

申请号：US180102

申请日：1994-01-11

Applicant: Francesco Pulvirenti ,  Roberto Gariboldi

Inventor： Francesco Pulvirenti ,  Roberto Gariboldi

IPC: H03K17/16 ,  H03K17/0412 ,  H03K17/0414 ,  H03K17/687 ,  H03K17/695

CPC classification number: H03K17/0414 ,  H03K17/04123 ,  H03K17/687

Abstract: A drive circuit for a field-effect transistor is disclosed, the field-effect transistor having a drain terminal connected to the positive pole of a voltage supply and a source terminal connected to a load. The drive circuit comprises a first transistor connected between the gate terminal of the field-effect transistor and the negative pole of the voltage supply for turning off the field-effect transistor. The first transistor is driven by an operational amplifier which has inverting and non-inverting teminals connected to the gate and source terminals of the field-effect transistor, respectively. Switches alternatively intercouple the field-effect transistor to either another voltage supply or the first transistor.

Abstract translation: 公开了一种用于场效应晶体管的驱动电路，场效应晶体管具有连接到电压源的正极的漏极端子和连接到负载的源极端子。 驱动电路包括连接在场效应晶体管的栅极端子和用于截止场效应晶体管的电压源的负极之间的第一晶体管。 第一晶体管由运算放大器驱动，运算放大器分别具有连接到场效应晶体管的栅极和源极端子的反相和非反相温度。 开关将场效应晶体管交替地耦合到另一个电压源或第一晶体管。

公开(公告)号：US5420525A

公开(公告)日：1995-05-30

申请号：US84727

申请日：1993-06-28

Applicant: Franco Maloberti ,  Gianmarco Marchesi ,  Guido Torelli

Inventor： Franco Maloberti ,  Gianmarco Marchesi ,  Guido Torelli

IPC: G11C11/417 ,  G11C7/10 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/094

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  H03K19/00361

Abstract: The switching noise generated by a data output buffer is greatly reduced by "precharging" the output node to an intermediate voltage during a system's "dead" time. This is done with a precharging output current pulse having a constant time derivative during a first time interval and a constant time derivative of opposite sign during a second time interval, before performing the actual switching with an output current having a constant time derivative, during a third time interval. The partial precharging with a controlled, triangular-shaped, output current pulse, avoids any abrupt change of output current and thus limits switching noise. The buffer of the invention is particularly useful in high-speed memory devices.

Abstract translation: 在系统的“死”时间内，通过将输出节点“预充电”为中间电压，大大减少了由数据输出缓冲器产生的开关噪声。 这是通过在第一时间间隔期间具有恒定时间导数的预充电输出电流脉冲和在第二时间间隔期间的具有相反符号的恒定时间导数之前，在执行具有恒定时间导数的输出电流的实际开关期间，在 第三次间隔。 用受控制的三角形输出电流脉冲进行部分预充电避免了输出电流的任何突然变化，从而限制了开关噪声。 本发明的缓冲器在高速存储器件中特别有用。

公开(公告)号：US5408148A

公开(公告)日：1995-04-18

申请号：US919606

申请日：1992-07-24

Applicant: Luigi Pascucci ,  Marco Olivo

Inventor： Luigi Pascucci ,  Marco Olivo

IPC: G11C11/417 ,  G11C7/06 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00 ,  G11C7/00 ,  G11C7/02

CPC classification number: G11C7/065 ,  G11C16/28

Abstract: The discriminating sensitivity of a sense amplifier and the speed of the circuit are increased by exploiting the difference of potential which develops across the output nodes of the two control circuits, employed for enabling/disabling current paths of the input network of the differential amplifier, as a virtual additional signal for the sensing differential amplifier, by employing said output potentials of the two control circuits as virtual reference potentials for the pair of input transistors of the differential amplifier during a discriminating phase of the reading cycle. Two pass-transistors driven by a control signal provide to force to ground potential the output nodes of said control circuits, thus reestablishing a correct ground reference potential of the amplifier, during the final phase of amplification and storage of the extracted datum in an output latch, as well as during the successive standby period. Alternative embodiments also include various anti-overshoot circuits.

Abstract translation: 读出放大器的鉴别灵敏度和电路速度通过利用两个控制电路的输出节点之间产生的电位差，用于使能/禁止差分放大器的输入网络的电流路径的差异作为 用于感测差分放大器的虚拟附加信号，通过在读取周期的识别阶段期间，将两个控制电路的所述输出电位用作差分放大器的一对输入晶体管的虚拟参考电位。 由控制信号驱动的两个通过晶体管提供强制接地电位的所述控制电路的输出节点，从而重新建立放大器的正确接地参考电位，在放大和放大输出锁存器中提取的数据的放大和存储的最后阶段期间 ，以及在连续的待命期间。 替代实施例还包括各种防过冲电路。

公开(公告)号：US5407852A

公开(公告)日：1995-04-18

申请号：US84971

申请日：1993-06-28

Applicant: Emilio G. Ghio ,  Giuseppe Meroni ,  Danilo Re ,  Livio Baldi

Inventor： Emilio G. Ghio ,  Giuseppe Meroni ,  Danilo Re ,  Livio Baldi

IPC: G11C17/12 ,  H01L21/8238 ,  H01L21/8246 ,  H01L27/092 ,  H01L27/112 ,  H01L21/70

CPC classification number: H01L27/11266 ,  H01L27/112

Abstract: ROM memories made in MOS or CMOS technology with LDD cells may be programmed advantageously in a relatively advanced stage of fabrication by decoupling an already formed drain region from the channel region of cells to be permanently made nonconductive (programmed) by implanting a dopant in an amount sufficient to invert the type of conductivity in a portion of the drain region adjacent to the channel region. In CMOS processes, the programming mask may be a purposely modified mask commonly used for implanting source/drain regions of transistors of a certain type of conductivity. By using high-energy implantation and a dedicated mask, the programming may be effected at even later stages of the fabrication process.

Abstract translation: 在具有LDD单元的MOS或CMOS技术中制造的ROM存储器可以通过将已经形成的漏极区域与细胞的沟道区域去耦合而被有利地编程在相对较先进的制造阶段中，以通过将量子点 足以颠倒与沟道区相邻的漏极区的一部分中的导电性。 在CMOS工艺中，编程掩模可以是通常用于注入某种导电性晶体管的源极/漏极区域的特意修改的掩模。 通过使用高能量注入和专用掩模，编程可以在制造过程的甚至后期进行。

公开(公告)号：US5401995A

公开(公告)日：1995-03-28

申请号：US99854

申请日：1993-07-30

Applicant: Ferdinando Lari ,  Pietro Erratico

Inventor： Ferdinando Lari ,  Pietro Erratico

IPC: H01L21/8222 ,  H01L27/06 ,  H03F1/32 ,  H03F3/45 ,  H01L29/72 ,  H01L27/02

CPC classification number: H03F1/3211

Abstract: An operational amplifier, of a type which comprises a differential cell transconductor input stage (2) incorporating a current mirror (5) provided with a pair of degenerative resistors (R9,R10) and a gain stage (7), driven directly by a transistor (Q12) of said mirror (5), has each degenerative resistor (R9,R10) formed within an epitaxial well wherewith a parasitic diode (D1,D2) is associated. Each diode (D1,D2) is connected in parallel with its corresponding resistor (R9,R10) to prevent the transistor (Q12) which drives the gain stage (7) from becoming saturated.

Abstract translation: 一种运算放大器，它是一种类型的运算放大器，它包括一个包含电流镜（5）的差分单元跨导体输入级（2），该电流反射镜（5）设有一对由晶体管直接驱动的退化电阻（R9，R10）和增益级（7） （5）的（Q12）具有形成在外延阱内的每个退化电阻器（R9，R10），其中寄生二极管（D1，D2）相关联。 每个二极管（D1，D2）与其对应的电阻器（R9，R10）并联连接，以防止驱动增益级（7）的晶体管（Q12）变得饱和。

公开(公告)号：US5394112A

公开(公告)日：1995-02-28

申请号：US35329

申请日：1993-03-22

Applicant: Roberto Alini ,  Francesco Rezzi ,  Gianfranco Vai ,  Marco Gregori

Inventor： Roberto Alini ,  Francesco Rezzi ,  Gianfranco Vai ,  Marco Gregori

IPC: H03H11/04 ,  H03H11/54 ,  G05F1/00 ,  G05F5/00

CPC classification number: H03H11/0422 ,  H03F1/302 ,  H03F3/45089 ,  H03F3/45484 ,  H03H11/54 ,  H03F2203/45418 ,  H03F2203/45564 ,  H03F2203/45594 ,  H03F2203/45622 ,  H03F2203/45626 ,  H03F2203/45628 ,  H03F2203/45674 ,  H03F2203/45702

Abstract: An integrated circuit transconductor stage which suppresses the dependence on temperature and production process variables of a differential transconductor stage. A negative feedback relation is used, where the output of the transconductor stage is connected to an additional current generator (which is referenced to a precision external resistor), to a capacitor, and also to the gate of a PMOS transistor which sources current to a polarization stage, which in turn sources current to the transconductor stage, or to multiple transconductor stages.

Abstract translation: 一种集成电路跨导级，其抑制了对差分跨导级的温度和生产工艺变量的依赖。 使用负反馈关系，其中跨导级的输出连接到附加电流发生器（以精密外部电阻器为基准），连接到电容器，以及连接到PMOS晶体管的栅极，PMOS晶体管将电流源源于 偏振级，其反过来将电流输送到跨导级，或者到多个跨导级。

公开(公告)号：US5393684A

公开(公告)日：1995-02-28

申请号：US988474

申请日：1992-12-10

Applicant: Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

Inventor： Paolo Ghezzi ,  Federico Pio ,  Carlo Riva

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/266

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/7883 ,  H01L27/115 ,  Y10S438/911 ,  Y10S438/981

Abstract: A method for forming thin oxide portions in electrically erasable and programmable read-only memory cells, including the use of the enhanced oxidation effect and the lateral diffusion of heavy doping, for obtaining a tunnel portion whose dimensions are smaller than the resolution of the photolithographic method used.

Abstract translation: 一种用于在电可擦除和可编程只读存储器单元中形成薄氧化物部分的方法，包括使用增强的氧化效应和重掺杂的横向扩散，以获得其尺寸小于光刻方法的分辨率的隧道部分 用过的。

公开(公告)号：US5376832A

公开(公告)日：1994-12-27

申请号：US29691

申请日：1993-03-11

Applicant: Roberto Gariboldi ,  Marcello Leone

Inventor： Roberto Gariboldi ,  Marcello Leone

IPC: H02M1/08 ,  H03F3/26 ,  H03K17/06 ,  H03K17/687 ,  H03L5/00

CPC classification number: H03K17/063 ,  H03K17/6871 ,  H03K17/6877

Abstract: A drive circuit includes a voltage source supplying a reference voltage at its output; a voltage elevating circuit connected to a supply voltage and to the output of the voltage source, and supplying at its output, under normal operating conditions, a drive voltage greater than the supply voltage and increasing with the reference voltage. The input of the voltage source is connected to the output of the voltage elevating circuit, and defines a positive feedback path resulting in an increase in the reference voltage corresponding to an increase in the drive voltage, and therefore results in a corresponding increase in the drive voltage up to a maximum permissible value, thus providing for a sufficient drive voltage for driving the gate-source junction of power MOS transistors, even in the presence of a low supply voltage.

Abstract translation: 驱动电路包括在其输出端提供参考电压的电压源; 连接到电源电压和电压源的输出端的电压提升电路，在正常工作条件下，在其输出端提供大于电源电压的驱动电压并用参考电压增加。 电压源的输入连接到电压升高电路的输出，并且定义正的反馈路径，导致对应于驱动电压的增加的参考电压的增加，因此导致驱动器的相应增加 电压达到最大允许值，因此即使在存在低电源电压的情况下也提供用于驱动功率MOS晶体管的栅 - 源结的足够的驱动电压。

公开(公告)号：US5376821A

公开(公告)日：1994-12-27

申请号：US812704

申请日：1991-12-23

Applicant: Santo Puzzolo ,  Raffaele Zambrano ,  Mario Paparo

Inventor： Santo Puzzolo ,  Raffaele Zambrano ,  Mario Paparo

IPC: H01L21/8249 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L27/07

CPC classification number: H01L27/0823 ,  H01L21/8222 ,  H01L27/0825

Abstract: A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N-epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides a connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

Abstract translation: 双极功率晶体管和低电压双极晶体管以集成结构组合在发射极开关或半谐振器配置中。 在具有非隔离部件的版本中，结构的部件彼此完全或部分地叠置，部分地在第一外延层中，部分地叠置在第二外延层中，并且低电压双极晶体管位于 双极功率晶体管因此是完全埋入的有源结构。 在具有隔离元件的版本中，N外延层中有两个P +区。 第一P +区域构成功率晶体管基极并且包围功率晶体管的N +发射极区域。 第二P +区域包围分别构成低压晶体管的集电极，发射极和基极区域的两个N +区域和一个P +区域。 芯片前面的金属化提供了低压晶体管的集电极触点和功率晶体管的发射极触点之间的连接。

公开(公告)号：US5367192A

公开(公告)日：1994-11-22

申请号：US165043

申请日：1993-12-06

Applicant: Angelo Massironi

Inventor： Angelo Massironi

IPC: H01L23/495 ,  H05K3/30 ,  H05K3/34 ,  H01L23/48 ,  H05K1/08

CPC classification number: H01L23/49548 ,  H05K3/308 ,  H01L2924/0002 ,  H05K2201/09709 ,  H05K2201/10696 ,  H05K2201/10757 ,  H05K2201/10871 ,  H05K3/3447

Abstract: This package for integrated devices, to be fixed on supporting plates, in particular on printed circuits, comprises contact pins to be inserted in holes of the supporting plates and to be soldered thereto. To prevent overturning of the package, which may lead to short circuits among the components, at least some of the contact pins are provided with protruding portions defining abutments cooperating with the supporting plate to limit the inclination of the package with respect to the plate.

Abstract translation: 用于固定在支撑板上，特别是印刷电路上的集成器件的封装包括插入支撑板的孔中并被焊接到其上的接触针。 为了防止包装翻倒，这可能导致部件之间的短路，至少一些接触销设置有突出部分，突出部分限定与支撑板配合的支座，以限制包装相对于板的倾斜度。