公开(公告)号：US08912653B2

公开(公告)日：2014-12-16

申请号：US13327563

申请日：2011-12-15

Applicant: Kah Wee Gan ,  Yonggang Jin ,  Anandan Ramasamy ,  Yun Liu

Inventor： Kah Wee Gan ,  Yonggang Jin ,  Anandan Ramasamy ,  Yun Liu

IPC: H01L23/52 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/00 ,  H01L21/311 ,  H01L23/31

CPC classification number: H01L21/3105 ,  H01L21/31116 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice.

Abstract translation: 半导体晶片具有形成在其上的集成电路和施加的顶部钝化层。 钝化层被图案化并选择性地蚀刻以暴露每个半导体管芯上的接触焊盘。 将晶片暴露于电离气体中，导致钝化层的上表面变粗糙，并使接触垫的上表面略微变糙。 切割晶片以形成多个具有粗糙化钝化层的半导体管芯。 多个半导体管芯被放置在粘合剂层上并形成重构的晶片。 形成再分布层，以完成具有用于建立半导体封装外部的电连接的电触头的半导体封装，之后将晶片单分割以分离晶片。

公开(公告)号：US20140293558A1

公开(公告)日：2014-10-02

申请号：US13852373

申请日：2013-03-28

Applicant: STMICROELECTRONICS PTE LTD.

Inventor： Wee Chin Judy Lim

IPC: H05K1/18 ,  H05K3/22

CPC classification number: H05K1/0215 ,  H05K9/0024 ,  H05K9/0039 ,  H05K2201/2018 ,  Y10T29/49124

Abstract: A lens mount is attached to a circuit board and covers electrical components on the circuit board. An electrically insulating device is positioned between the lens mount and the circuit board. The circuit board includes a grounding pad adjacent the electrically insulating device. The lens mount includes an aperture aligned with the grounding pad and the electrically insulating device. A conductive glue is dispensed into the aperture to electrically ground the lens mount to the grounding pad. The electrically insulating device seals the conductive glue from the electrical components. A method of grounding a lens mount to a circuit board is provided.

Abstract translation: 镜头座安装在电路板上并覆盖电路板上的电气部件。 电绝缘装置位于透镜支架和电路板之间。 电路板包括邻近电绝缘装置的接地垫。 透镜座包括与接地垫和电绝缘装置对准的孔。 将导电胶分配到孔中以将透镜安装座电接地到接地垫。 电绝缘装置将导电胶从电气部件密封。 提供了一种将透镜座连接到电路板的方法。

公开(公告)号：US20140291867A1

公开(公告)日：2014-10-02

申请号：US13853496

申请日：2013-03-29

Applicant: STMICROELECTRONICS PTE LTD.

Inventor： Yohanes Bintang

IPC: H01L21/66 ,  H01L23/498

CPC classification number: H01L22/14 ,  H01L22/20 ,  H01L23/3128 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: A semiconductor package includes an RFID chip positioned between a first die and a second die attached to a support substrate. The RFID chip is free of electrical connections to the dice and the support substrate. The RFID chip is sized to correspond to an interposer board. Data pertaining to operating characteristics of the dice are stored to and read from the RFID chip during back-end processing to determine abnormalities and improve yield. Said data may be stored to a database corresponding to the RFID chip in the package. A method of making a semiconductor package having an RFID chip positioned between dice is provided. The package is traceable by customers via the data stored to the RFID chip and the database.

Abstract translation: 半导体封装包括位于第一管芯和附接到支撑衬底的第二管芯之间的RFID芯片。 RFID芯片没有与骰子和支撑基板的电连接。 RFID芯片的大小对应于插入板。 关于骰子的操作特性的数据在后端处理期间被存储到RFID芯片并从其读取，以确定异常并提高产量。 所述数据可以存储在与包装中的RFID芯片相对应的数据库中。 提供了一种制造具有位于晶片之间的RFID芯片的半导体封装的方法。 该包可以通过存储到RFID芯片和数据库的数据由客户追踪。

公开(公告)号：US20140291782A1

公开(公告)日：2014-10-02

申请号：US13853645

申请日：2013-03-29

Applicant: STMICROELECTRONICS PTE LTD.

Inventor： Kim-Yong Goh ,  Yiyi Ma ,  Wei Zhen Goh

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0058 ,  B81C2203/0109 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/00014

Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.

Abstract translation: 集成电路封装的方法和装置。 封装的装置可以包括集成电路，包括图案化表面的第一包装部件和第二包装部件。 第一包装部件的图案化表面可以粘合地耦合到第二包装部件的表面或集成电路的表面。 集成电路可以至少部分地封装在第一和第二封装部件之间。 包装方法可以包括图案化集成电路封装的封装部件的表面。 包装部件的表面可以用于粘合地耦合到第二部件以至少部分地封装集成电路封装中的集成电路。

公开(公告)号：US20140175649A1

公开(公告)日：2014-06-26

申请号：US13727206

申请日：2012-12-26

Applicant: STMICROELECTRONICS PTE. LTD

Inventor： Yonggang Jin ,  Yun Liu ,  Yaohuang Huang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L24/19 ,  H01L23/3128 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via.

Abstract translation: 电子器件可以包括其中具有第一导电通孔的底部互连层。 电子设备还可以包括由所述底部互连层承载的集成电路（IC）和在底部互连层上并围绕IC的封装材料。 封装层可以具有与第一导电通孔对准的第二导电通孔。 第二导电通孔的横截面积可以大于第一导电通孔的横截面面积。

公开(公告)号：US08733871B2

公开(公告)日：2014-05-27

申请号：US13281417

申请日：2011-10-25

Applicant: Jin Hao Chia ,  Yong Peng Yeo ,  Wei Leong Lim ,  Shi Min Veronica Goh ,  Mei Yu Muk

Inventor： Jin Hao Chia ,  Yong Peng Yeo ,  Wei Leong Lim ,  Shi Min Veronica Goh ,  Mei Yu Muk

IPC: B41J29/38 ,  B41J2/05

CPC classification number: H01L21/02071 ,  H01L21/32134 ,  H01L21/32138 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76865

Abstract: A process for forming a metal interconnection in an integrated circuit includes forming a first metal layer and a second metal layer on the first metal layer. Photoresist is placed on the second metal layer and patterned to form a mask. The second metal layer is etched. The mask is then removed and the first metal layer is patterned with the second metal layer acting as mask for the first metal layer.

Abstract translation: 在集成电路中形成金属互连的工艺包括在第一金属层上形成第一金属层和第二金属层。 将光刻胶放置在第二金属层上并图案化以形成掩模。 蚀刻第二金属层。 然后去除掩模，并且第一金属层被图案化，第二金属层用作第一金属层的掩模。

公开(公告)号：US20140133215A1

公开(公告)日：2014-05-15

申请号：US14150676

申请日：2014-01-08

Applicant: STMicroelectronics Pte Ltd.

Inventor： Olivier Le Neel

IPC: G11C13/00

CPC classification number: G11C13/0002 ,  G11C11/21 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/33 ,  G11C2213/71

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.

Abstract translation: 形成集成电路，其具有位于半导体衬底上方的电介质堆叠中的存储器单元的阵列。 每个存储单元具有两个可调电阻器和两个加热元件。 电介质材料将加热元件与可调电阻分开。 一个加热元件通过加热来改变其中一个电阻器的电阻以将数据写入存储单元。 另一个加热元件通过加热来改变另一个电阻器的电阻，从而擦除来自存储单元的数据。

公开(公告)号：US20140111875A1

公开(公告)日：2014-04-24

申请号：US13657542

申请日：2012-10-22

Applicant: STMICROELECTRONICS PTE LTD.

Inventor： Laurent Herard

IPC: B29D11/00 ,  B05D5/06 ,  B23P17/04 ,  G02B3/00

CPC classification number: B29D11/00298 ,  G02B3/0031 ,  G02B3/0068 ,  G02B3/0075 ,  Y10T29/4998

Abstract: A method comprises depositing an optical filter layer on a glass wafer, then cutting the wafer into dice. The dice are positioned on a carrier and encapsulated in a molding compound to form a reconstituted wafer, and the wafer is back-ground and polished. Lens faces are positioned on opposing surfaces of the glass dice and spacers are positioned on one side of the wafer. The wafer is then cut into lens modules, each having two side-by-side lenses with an opaque molding compound barrier between. The individual modules are attached to devices that require dual lenses, such as, e.g., proximity sensors that use a light source and a light receiver or detector.

Abstract translation: 一种方法包括在玻璃晶片上沉积光学过滤层，然后将晶片切割成骰子。 将骰子定位在载体上并封装在模制化合物中以形成重构的晶片，并且将晶片进行背面和抛光。 透镜面定位在玻璃骰子的相对表面上，并且间隔物位于晶片的一侧。 然后将晶片切成透镜模块，每个透镜模块具有两个并排的透镜，其间具有不透明的模制化合物屏障。 各个模块附接到需要双透镜的装置，例如使用光源和光接收器或检测器的接近传感器。

公开(公告)号：US20140077667A1

公开(公告)日：2014-03-20

申请号：US13622556

申请日：2012-09-19

Applicant: STMICROELECTRONICS PTE LTD.

Inventor： ROMOLO BACTASA

IPC: H01L21/683 ,  B23P17/00 ,  H01L21/673

CPC classification number: H01L21/67309 ,  H01L21/67303 ,  H05K13/0084 ,  Y10T29/49826

Abstract: A wafer handling station includes a housing defining a chamber, and a wafer cassette assembly positionable in the chamber. The wafer cassette assembly includes a vertical support, and cassette members carried by the vertical support in spaced relation. Each cassette member includes a base coupled to the vertical support, wafer contact pads on an upper surface of the base and configured to support a wafer thereon, and a pair of wafer brackets carried by the base and configured to engage respective edges of the wafer to laterally confine the wafer.

Abstract translation: 晶片处理站包括限定腔室的壳体和可定位在腔室中的晶片盒组件。 晶片盒组件包括垂直支撑件和由垂直支撑件以间隔关系承载的盒构件。 每个盒构件包括联接到垂直支撑件的基座，在基座的上表面上的晶片接触垫，并且被配置为在其上支撑晶片，以及一对晶片支架，其由基座承载并且被配置为将晶片的相应边缘接合到 横向限制晶片。

公开(公告)号：US08664746B2

公开(公告)日：2014-03-04

申请号：US13237671

申请日：2011-09-20

Applicant: Janusz Karol Korycinski ,  Wanliang Wen

Inventor： Janusz Karol Korycinski ,  Wanliang Wen

IPC: H01L29/30

CPC classification number: H01L21/3226 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/1203 ,  H01L29/32 ,  H01L29/78

Abstract: A silicon on insulater (SOI) wafer is provided. A dielectric layer is formed on an active silicon substrate of the wafer. The dielectric layer is patterned and etched to expose selected portions of the silicon substrate. Impurities are then introduced into the exposed portions of the silicon substrate to act as gettering regions. The dielectric layer is then removed and an epitaxial layer of silicon is grown on the silicon substrate. Trenches are etched in the epitaxial layer of silicon through the gettering regions, partially removing the gettering regions and any contaminants contained therein. Remaining portions of the gettering regions still act as gettering regions during subsequent process steps.

Abstract translation: 提供了一种绝缘硅（SOI）晶圆。 在晶片的有源硅衬底上形成电介质层。 对电介质层进行图案化和蚀刻以暴露硅衬底的选定部分。 然后将杂质引入硅衬底的暴露部分中以用作吸杂区域。 然后去除电介质层，并在硅衬底上生长外延硅层。 通过吸气区域在硅的外延层中蚀刻沟槽，部分地去除吸气区域和其中包含的任何污染物。 吸附区域的剩余部分在后续工艺步骤中仍然作为吸气区域。