-
公开(公告)号：US20210232871A1
公开(公告)日：2021-07-29
申请号：US17258015
申请日：2019-06-20
Applicant: Optimum Semiconductor Technologies Inc.
Inventor： Sabin Daniel IANCU , John GLOSSNER , Beinan WANG
Abstract: A system and method relating to object detection using multiple sensor devices include receiving a range data comprising a plurality of points, each of plurality of points being associated with an intensity value and a depth value, determining, based on the intensity values and depth values of the plurality of points, abounding box surrounding a cluster of points among the plurality of points, receiving a video image comprising an array of pixels, determining a region in the video image corresponding to the bounding box, and applying a first neural network to the region to determine an object captured by the range data and the video image.
-
公开(公告)号：US10908909B2
公开(公告)日：2021-02-02
申请号：US15155570
申请日：2016-05-16
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan
Abstract: A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include switching mode logic to switch between the first mode and the second mode.
-
公开(公告)号：US10514915B2
公开(公告)日：2019-12-24
申请号：US15086711
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC: G06F9/30 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F9/32 , G06F9/355 , G06F12/0862 , G06F12/1027 , G06F3/06
Abstract: A computer processor with an address register file is disclosed. The computer processor may include a memory. The computer processor may further include a general purpose register file comprising at least one general purpose register. The computer processor may further include an address register file comprising at least one address register. The computer processor may further include having access to the memory, the general purpose register file, and the address register file. The processing logic may execute a memory access instruction that accesses one or more memory locations in the memory at one or more corresponding addresses computed by retrieving the value of an address register of the at least one register of the address register file specified in the instruction and adding a displacement value encoded in the instruction.
-
公开(公告)号：US10339095B2
公开(公告)日：2019-07-02
申请号：US14716285
申请日：2015-05-19
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola , Vitaly Kalashnikov , Sitij Agrawal
Abstract: A computer processor is disclosed. The computer processor comprises a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor further comprises processing logic configured to operate on the varying number of elements in the vector register file using one or more digital signal processing instructions. The computer processor may be implemented as a monolithic integrated circuit.
-
25.发明授权公开(公告)号：US10339094B2
公开(公告)日：2019-07-02
申请号：US14716216
申请日：2015-05-19
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola , Vitaly Kalashnikov , Sitij Agrawal
Abstract: A computer processor is disclosed. The computer processor comprises one or more processor resources. The computer processor further comprises a plurality of hardware thread units coupled to the one or more processor resources. The computer processor may be configured to permit simultaneous access to the one or more processor resources by only a subset of hardware thread units of the plurality of hardware thread units. The number of hardware threads in the subset may be less than the total number of hardware threads of the plurality of hardware thread units.
-
Patent Agency Ranking
26.发明授权公开(公告)号：US09792116B2
公开(公告)日：2017-10-17
申请号：US15087204
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC: G06F12/10 , G06F9/30 , G06F3/06 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F12/0862 , G06F9/32 , G06F9/355
CPC classification number: G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
Abstract: A computer processor that implements pre-translation of virtual addresses with target registers is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual instruction address, the virtual instruction address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.
-
27.发明授权公开(公告)号：US09766895B2
公开(公告)日：2017-09-19
申请号：US14539116
申请日：2014-11-12
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Shenghong Wang , C. John Glossner , Gary J. Nacer
CPC classification number: G06F9/3826 , G06F9/3818 , G06F9/382 , G06F9/3822 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/46
Abstract: A computing device determines that a current software thread of a plurality of software threads having an issuing sequence does not have a first instruction waiting to be issued to a hardware thread during a clock cycle. The computing device identifies one or more alternative software threads in the issuing sequence having instructions waiting to be issued. The computing device selects, during the clock cycle by the computing device, a second instruction from a second software thread among the one or more alternative software threads in view of determining that the second instruction has no dependencies with any other instructions among the instructions waiting to be issued. Dependencies are identified by the computing device in view of the values of a chaining bit extracted from each of the instructions waiting to be issued. The computing device issues the second instruction to the hardware thread.
-
公开(公告)号：US09558000B2
公开(公告)日：2017-01-31
申请号：US14539342
申请日：2014-11-12
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： C. John Glossner , Gary J. Nacer , Murugappan Senthilvelan , Vitaly Kalashnikov , Arthur J. Hoane , Paul D'Arcy , Sabin D. Iancu , Shenghong Wang
CPC classification number: G06F9/3851 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3885 , G06F9/46
Abstract: A processing device identifies a set of software threads having instructions waiting to issue. For each software thread in the set of the software threads, the processing device binds the software thread to an available hardware context in a set of hardware contexts and stores an identifier of the available hardware context bound to the software thread to a next available entry in an ordered list. The processing device reads an identifier stored in an entry of the ordered list. Responsive to an instruction associated with the identifier having no dependencies with any other instructions among the instructions waiting to issue, the processing device issues the instruction waiting to issue to the hardware context associated with the identifier.
Abstract translation: 处理设备识别具有等待发布的指令的一组软件线程。 对于软件线程集合中的每个软件线程，处理设备将软件线程绑定到一组硬件上下文中的可用硬件上下文，并将绑定到软件线程的可用硬件上下文的标识符存储到下一个可用条目中 有序列表。 处理装置读取存储在有序列表的条目中的标识符。 响应于等待发布的指令中与标识符相关联的与任何其他指令无关的指令，处理设备发出等待发布到与标识符相关联的硬件上下文的指令。
-
公开(公告)号：US12165030B2
公开(公告)日：2024-12-10
申请号：US17351434
申请日：2021-06-18
Applicant: Optimum Semiconductor Technologies Inc.
Inventor： Mayan Moudgill , John Glossner
Abstract: A system and method include an accelerator circuit comprising an input circuit block, a filter circuit block, a post-processing circuit block, and an output circuit block and a processor to initialize the accelerator circuit, determining tasks of a neural network application to be performed by at least one of the input circuit block, the filter circuit block, the post-processing circuit block, or the output circuit block, assign each of the tasks to a corresponding one of the input circuit block, the filter circuit block, the post-processing circuit block, or the output circuit block, instruct the accelerator circuit to perform the tasks, and execute the neural network application based on results received from the accelerator circuit completing performance of the tasks.
-
30.发明申请公开(公告)号：US20220129262A1
公开(公告)日：2022-04-28
申请号：US17427843
申请日：2020-02-20
Applicant: Optimum Semiconductor Technologies Inc.
Inventor： Mayan MOUDGILL , Pablo BALZOLA , Murugappan SENTHIVELAN , Vaidyanathan RAMDURAI , Sitij AGRAWAL
Abstract: A system and an accelerator circuit including a register file comprising instruction registers to store an instruction for evaluating an elementary function, and data registers comprising a first data register to store an input value. The accelerator circuit further includes a successive cumulative rotation circuit comprising a reconfigurable inner stage to perform a successive cumulative rotation recurrence, and a determination circuit to determine a type of the elementary function based on the instruction, and responsive to determining that the input value is a fixed-point number, configure the reconfigurable inner stage to a configuration for evaluating the type of the elementary function, wherein the successive cumulative rotation circuit is to calculate an evaluation of the elementary function using the reconfigurable inner stage performing the successive cumulative rotation recurrence.
-
-
-
-
-
-
-
-
-
Search Results
41
records
(took 0.034 seconds)
