公开(公告)号：US20130127055A1

公开(公告)日：2013-05-23

申请号：US13434691

申请日：2012-03-29

Applicant: Chien-An CHEN ,  Wen-Jiun LIU ,  Chun-Chieh LIN ,  Hung-Wen SU ,  Ming-Hsing TSAI ,  Syun-Ming JANG

Inventor： Chien-An CHEN ,  Wen-Jiun LIU ,  Chun-Chieh LIN ,  Hung-Wen SU ,  Ming-Hsing TSAI ,  Syun-Ming JANG

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76882 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The mechanisms of forming an interconnect structures described above involves using a reflowed conductive layer. The reflowed conductive layer is thicker in smaller openings than in wider openings. The mechanisms may further involve forming a metal cap layer over the reflow conductive layer, in some embodiments. The interconnect structures formed by the mechanisms described have better electrical and reliability performance.

Abstract translation: 形成上述互连结构的机理涉及使用回流导电层。 较小的开口中的回流导电层比较宽的开口厚。 在一些实施例中，这些机构还可以包括在回流导电层上形成金属盖层。 由所述机构形成的互连结构具有更好的电气和可靠性性能。

公开(公告)号：US20110256681A1

公开(公告)日：2011-10-20

申请号：US13166481

申请日：2011-06-22

Applicant: Chun-Chieh Lin ,  Wei-Hua Hsu ,  Yu-En Percy Chang ,  Chung Li Chang ,  Chi-Feng Cheng ,  Win Hung ,  Kishimoto Ko

Inventor： Chun-Chieh Lin ,  Wei-Hua Hsu ,  Yu-En Percy Chang ,  Chung Li Chang ,  Chi-Feng Cheng ,  Win Hung ,  Kishimoto Ko

IPC: H01L21/336

CPC classification number: H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A method includes forming a gate stack over a semiconductor substrate, and forming a first silicon germanium (SiGe) region in the semiconductor substrate and adjacent the gate stack. The first SiGe region has a first atomic percentage of germanium to germanium and silicon. A second SiGe region is formed over the first SiGe region. The second SiGe region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is lower than the first atomic percentage, wherein the first and the second SiGe regions form a source/drain stressor of a metal-oxide-semiconductor (MOS) device.

Abstract translation: 一种方法包括在半导体衬底上形成栅叠层，并在半导体衬底中形成第一硅锗（SiGe）区，并邻近栅叠。 第一个SiGe区域具有锗与锗和硅的第一原子百分比。 在第一SiGe区域上形成第二SiGe区域。 第二SiGe区域具有锗与锗和硅的第二原子百分比。 第二原子百分比低于第一原子百分比，其中第一和第二SiGe区域形成金属氧化物半导体（MOS）器件的源极/漏极应力源。

公开(公告)号：US07646068B2

公开(公告)日：2010-01-12

申请号：US11483913

申请日：2006-07-10

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L29/76 ,  H01L29/00

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

Abstract translation: 半导体芯片包括其中设置有第一和第二有源区的半导体衬底126。 电阻器124形成在第一有源区域中，并且电阻器124包括形成在两个端子136之间的掺杂区域128.应变沟道晶体管132形成在第二有源区域中。 该晶体管包括第一和第二应力源141，该第一和第二应力器141形成在与基片相反的相邻的应变通道区域143之间。

公开(公告)号：US20090035937A1

公开(公告)日：2009-02-05

申请号：US12186936

申请日：2008-08-06

Applicant: Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

Inventor： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

IPC: H01L21/44

CPC classification number: H01L23/53238 ,  H01L21/2885 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.

Abstract translation: 提供了具有减小的小丘形成的半导体互连结构及其形成方法。 半导体互连结构包括形成在电介质层中的导体。 导体包括至少三个子层，其中相邻子层中杂质浓度的比优选大于约2。

公开(公告)号：US07459756B2

公开(公告)日：2008-12-02

申请号：US11467980

申请日：2006-08-29

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC: H01L29/76

CPC classification number: H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

Abstract translation: 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。

公开(公告)号：US07335929B2

公开(公告)日：2008-02-26

申请号：US10967917

申请日：2004-10-18

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC: H01L31/00

CPC classification number: H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802

Abstract: A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.

Abstract translation: 晶体管结构包括覆盖衬底区域的沟道区域。 衬底区域包括具有第一晶格常数的第一半导体材料。 沟道区域包括具有第二晶格常数的第二半导体材料。 源极区和漏极区相对地邻近沟道区，并且源极和漏极区的顶部包括第一半导体材料。 栅极电介质层覆盖沟道区，栅电极覆盖在栅介质层上。

公开(公告)号：US07312136B2

公开(公告)日：2007-12-25

申请号：US10899270

申请日：2004-07-26

Applicant: Chien-Chao Huang ,  Yee-Chia Yeo ,  Kuo-Nan Yang ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chien-Chao Huang ,  Yee-Chia Yeo ,  Kuo-Nan Yang ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L21/20

CPC classification number: H01L21/3247 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/76259 ,  H01L29/1054

Abstract: A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1-x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1-x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.

Abstract translation: 实现了制造具有用于增加电子和空穴迁移率的应变硅层的SOI晶片的方法。 该方法在种子晶片上形成多孔硅层。 使用H 2 H 2退火在多孔硅上形成光滑表面。 沉积无应变的（松弛的）外延的Si 1 x 1-x层，并形成结合层。 然后将种子晶片结合到在表面上具有绝缘体的手柄晶片。 使用喷涂蚀刻来蚀刻多孔Si层，导致SOI处理晶片，其具有在松弛的Si 1 x 1-x x上的多孔Si层的部分。 然后将手柄晶片在H 2 2中退火以将多孔Si转化为SOI晶片的松弛SiGe层上的平滑应变Si层。

公开(公告)号：US20070195168A1

公开(公告)日：2007-08-23

申请号：US11707967

申请日：2007-02-20

Applicant: Chi-Hsien Wang ,  Wen-Ming Huang ,  Wei-Song Yeh ,  Chun-Chieh Lin ,  Kuan-Chou Chen

Inventor： Chi-Hsien Wang ,  Wen-Ming Huang ,  Wei-Song Yeh ,  Chun-Chieh Lin ,  Kuan-Chou Chen

IPC: H04N5/225

CPC classification number: H04N19/184 ,  H04N19/91

Abstract: A web camera includes an image sensor, which takes an external image; a sensor interface, which is connected to the mage sensor to receive and convert the image taken by the image sensor into digital image data; at least one compression module, which is connected to the sensor interface to receive and compress the digital image data into compressed image data; and a USB interface, which is connected to the compression module to output the compressed image data to a host device having a USB interface port, such as a computer and a USB OTG device, for storage, playing back and other applications.

Abstract translation: 网络摄像机包括拍摄外部图像的图像传感器; 传感器接口，其连接到法师传感器，以将图像传感器拍摄的图像接收并转换为数字图像数据; 至少一个压缩模块，其连接到传感器接口以将数字图像数据接收并压缩成压缩图像数据; 以及USB接口，其连接到压缩模块以将压缩的图像数据输出到具有诸如计算机和USB OTG设备的USB接口端口的主机设备，用于存储，回放和其他应用。

公开(公告)号：US07172933B2

公开(公告)日：2007-02-06

申请号：US10864952

申请日：2004-06-10

Applicant: Yi-Chun Huang ,  Bow-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Hun-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

Inventor： Yi-Chun Huang ,  Bow-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Hun-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/20 ,  H01L21/205 ,  H01L21/425 ,  H01L21/265 ,  H01L21/44 ,  H01L21/28 ,  H01L21/4763 ,  H01L21/3205

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract translation: 已经开发了通过使用相邻和周围的硅 - 锗形状在应变硅层中形成用于MOSFET器件的沟道区域的方法。 该方法同时形成导电栅极结构的顶部中的凹部并且在半导体衬底的不被栅极结构占据的部分中，或者位于导电栅极结构的侧面上的虚设间隔物。 选择性限定的凹槽将用于随后容纳硅锗形状，其中硅 - 锗形状位于半导体衬底的凹陷中，从而诱导期望的应变通道区域。 导电栅极结构和半导体衬底部分的凹陷减少了在合金层的外延生长期间跨越侧壁间隔物的硅 - 锗桥接的风险，从而降低了栅极到衬底泄漏或短路的风险。

公开(公告)号：US07057237B2

公开(公告)日：2006-06-06

申请号：US10798063

申请日：2004-03-11

Applicant: Howard Chih Hao Wang ,  Chenming Hu ,  Chun-Chieh Lin

Inventor： Howard Chih Hao Wang ,  Chenming Hu ,  Chun-Chieh Lin

IPC: H01L21/266

CPC classification number: H01L29/6656 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/1052

Abstract: A method is described for forming three or more spacer widths in transistor regions on a substrate. In one embodiment, different silicon nitride thicknesses are formed above gate electrodes followed by nitride etching to form spacers. Optionally, different gate electrode thicknesses may be fabricated and a conformal oxide layer is deposited which is subsequently etched to form different oxide spacer widths. A third embodiment involves a combination of different gate electrode thickness and different nitride thicknesses. A fourth embodiment involves selectively thinning an oxide layer over certain gate electrodes before etching to form spacers. Therefore, spacer widths can be independently optimized for different transistor regions on a substrate to enable better drive current in transistors with narrow spacers and improved SCE control in neighboring transistors with wider spacers. Better drive current is also obtained in transistors with shorter polysilicon thickness.

Abstract translation: 描述了用于在衬底上的晶体管区域中形成三个或更多个间隔物宽度的方法。 在一个实施例中，在栅电极之上形成不同的氮化硅厚度，随后氮化物蚀刻以形成间隔物。 可选地，可以制造不同的栅极电极厚度，并且沉积保形氧化物层，其随后被蚀刻以形成不同的氧化物间隔物宽度。 第三实施例涉及不同栅电极厚度和不同氮化物厚度的组合。 第四实施例涉及在蚀刻之前在某些栅电极上选择性地稀薄氧化物层以形成间隔物。 因此，可以对衬底上的不同晶体管区域独立地优化间隔物宽度，以在具有窄间隔物的晶体管中实现更好的驱动电流并且在具有较宽间隔物的相邻晶体管中改善SCE控制。 更薄的多晶硅厚度的晶体管也可获得更好的驱动电流。