公开(公告)号：US20070112176A1

公开(公告)日：2007-05-17

申请号：US10551780

申请日：2004-04-02

Applicant: Motoharu Seiki ,  Ikuo Yana ,  Takanori Aoki ,  Junko Yasuda ,  Hiroshi Kikuchi ,  Emi Ishida

Inventor： Motoharu Seiki ,  Ikuo Yana ,  Takanori Aoki ,  Junko Yasuda ,  Hiroshi Kikuchi ,  Emi Ishida

IPC: A61K9/127 ,  C07K14/82

CPC classification number: A61K31/704 ,  A61K9/127 ,  A61K47/6871 ,  A61K47/6901 ,  A61K48/00

Abstract: A lipid membrane structure containing an anti-membrane-type matrix metalloproteinase monoclonal antibody such as an anti-MT1-MMP monoclonal antibody as a component of the lipid membrane structure. Said structure can be utilized as a drug delivery system for efficiently delivering a medicinally active ingredient and/or a gene to tumor cells, neoplastic vessel and the like in which a membrane-type matrix metalloproteinase (MT-MMP) is expressed.

Abstract translation: 含有抗 - 膜型基质金属蛋白酶单克隆抗体如抗MT1-MMP单克隆抗体作为脂质膜结构的组分的脂质膜结构。 所述结构可用作药物递送系统，用于向其中表达膜型基质金属蛋白酶（MT-MMP）的肿瘤细胞，肿瘤血管等有效递送药物活性成分和/或基因。

公开(公告)号：US06642134B2

公开(公告)日：2003-11-04

申请号：US09401797

申请日：1999-09-22

Applicant: Emi Ishida ,  Scott Luning

Inventor： Emi Ishida ,  Scott Luning

IPC: H01L213205

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/823864 ,  H01L29/6656

Abstract: A semiconductor device is provided with semiconducting sidewall spacers used in the formation of source/drain regions. The semiconducting sidewall spacers also reduce the possibility of suicide shorting through shallow source/drain junctions. Embodiments include doping the semiconducting sidewall spacers so that they serve as a source of impurities for forming source/drain extensions during activation annealing.

Abstract translation: 半导体器件设置有用于形成源极/漏极区域的半导体侧壁间隔物。 半导体侧壁间隔物还减少了通过浅源极/漏极结的自杀性短路的可能性。 实施例包括掺杂半导体侧壁间隔物，使得它们用作在激活退火期间形成源极/漏极延伸的杂质源。

公开(公告)号：US06403433B1

公开(公告)日：2002-06-11

申请号：US09397217

申请日：1999-09-16

Applicant: Bin Yu ,  Jonathan Kluth ,  Emi Ishida

Inventor： Bin Yu ,  Jonathan Kluth ,  Emi Ishida

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/78618

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on an SOI substrate. The MOSFETs include elevated source and drain regions. The elevated source and drain regions are amorphized before doping. Neutral ion species can be utilized to amorphize the elevated source and drain region. Dopants are activated in a low-temperature rapid thermal anneal process.

Abstract translation: 超大规模集成（ULSI）电路包括SOI衬底上的MOSFET。 MOSFET包括升高的源极和漏极区域。 在掺杂之前，升高的源极和漏极区非晶化。 中性离子物质可用于使提升的源极和漏极区域非晶化。 掺杂剂在低温快速热退火工艺中被激活。

公开(公告)号：US06277698B1

公开(公告)日：2001-08-21

申请号：US09382580

申请日：1999-08-25

Applicant: Emi Ishida ,  Dong-Hyuk Ju ,  David Wu

Inventor： Emi Ishida ,  Dong-Hyuk Ju ,  David Wu

IPC: H01L21336

CPC classification number: H01L29/66583 ,  H01L21/823842

Abstract: A semiconductor device is provided with a gate electrode having a substantially rectangular profile by forming a dielectric film prior to depositing the gate electrode layer. The dielectric film is patterned and etched to form regions having a rectangular profile separated by open regions. A gate electrode layer is then deposited followed by planarization to form gate electrodes having a substantially rectangular profile.

Abstract translation: 通过在沉积栅极电极层之前形成电介质膜，半导体器件设置有具有大致矩形轮廓的栅电极。 对电介质膜进行图案化和蚀刻以形成具有由开放区域分开的矩形轮廓的区域。 然后沉积栅极电极层，然后平坦化以形成具有基本上矩形轮廓的栅电极。

公开(公告)号：US6143632A

公开(公告)日：2000-11-07

申请号：US993049

申请日：1997-12-18

Applicant: Emi Ishida ,  Peng Fang

Inventor： Emi Ishida ,  Peng Fang

IPC: H01L21/265 ,  H01L21/28 ,  H01L29/32 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76

CPC classification number: H01L21/28185 ,  H01L21/26506 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/32 ,  H01L29/4983 ,  H01L29/518

Abstract: A semiconductor device having reduced hot carrier degradation is achieved by doping the semiconductor substrate and gate oxide with deuterium. A conventional semiconductor device is formed with sequentially deposited metal layers and dielectric layers and a topside protective dielectric layer deposited thereon. Deuterium is introduced to the semiconductor device by using deuterium-containing reactants in at least one of the semiconductor manufacturing steps to passivate dangling silicon bonds at the silicon/oxide interface region.

Abstract translation: 具有减少的热载流子劣化的半导体器件通过用氘掺杂半导体衬底和栅极氧化物来实现。 常规的半导体器件形成有顺序沉积的金属层和介电层以及沉积在其上的顶侧保护电介质层。 通过在半导体制造步骤中的至少一个中使用含氘的反应物，在硅/氧化物界面区域钝化悬挂的硅键，将氘引入半导体器件。

公开(公告)号：US5885904A

公开(公告)日：1999-03-23

申请号：US799235

申请日：1997-02-14

Applicant: Sunil Mehta ,  Emi Ishida ,  Xiao-Yu Li

Inventor： Sunil Mehta ,  Emi Ishida ,  Xiao-Yu Li

IPC: H01L21/311 ,  H01L21/316 ,  H01L21/461 ,  H01L21/31

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/0231 ,  H01L21/02312 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/31662

Abstract: A method for forming a uniform and reliable oxide layer on the surface of a semiconductor substrate using projection gas immersion laser doping (P-GILD) is provided. A semiconductor substrate is immersed in an oxide enhancing compound containing atmosphere. The oxide enhancing compound containing atmosphere may include phosphorus, arsenic, boron or an equivalent. A 308 nm excimer laser is then applied to a portion of the substrate to induce incorporation of the oxide enhancing compound into a portion of the substrate. The deposition depth is dependent upon the strength of the laser energy directed at the surface of the substrate. A uniform and reliable oxide layer is then formed on the surface of the substrate by heating the substrate. The laser may be applied with a reflective reticle or mask formed on the substrate. An E.sup.2 PROM memory cell having a program junction region in a silicon substrate is also provided. An oxide layer is positioned between a program junction and a floating gate. The oxide layer is formed by a single or multiple thermal oxidation step(s) to have at least a first oxide thickness due to a GILD oxide enhancing compound underlying a region of the oxide having at least the first oxide thickness.

Abstract translation: 提供了使用投影气体浸渍激光掺杂（P-GILD）在半导体衬底的表面上形成均匀且可靠的氧化物层的方法。 将半导体衬底浸入含氧化物增强化合物的气氛中。 含氧化物增强化合物的气氛可以包括磷，砷，硼或等价物。 然后将308nm准分子激光器施加到衬底的一部分以诱导氧化物增强化合物掺入衬底的一部分中。 沉积深度取决于指向衬底表面的激光能量的强度。 然后通过加热衬底在衬底的表面上形成均匀且可靠的氧化物层。 可以在基板上形成反射型掩模版或掩模来施加激光。 还提供了具有硅衬底中的程序接合区的E2PROM存储单元。 氧化物层位于程序结和浮动栅之间。 通过单个或多个热氧化步骤形成氧化物层，以至少具有第一氧化物厚度，这是由于至少具有第一氧化物厚度的氧化物区域下面的GILD氧化物增强化合物。

公开(公告)号：US06756600B2

公开(公告)日：2004-06-29

申请号：US09252845

申请日：1999-02-19

Applicant: Che-Hoo Ng ,  Emi Ishida ,  Jaime M. Reyes ,  Jinning Liu ,  Sandeep Mehta

Inventor： Che-Hoo Ng ,  Emi Ishida ,  Jaime M. Reyes ,  Jinning Liu ,  Sandeep Mehta

IPC: H01J3708

CPC classification number: H01J27/08 ,  H01J37/08 ,  H01J2237/31701

Abstract: A method of increasing ion source lifetime in an ion implantation system uses the introduction of an inert gas, such as argon or xenon, into the halide-containing source gas. Inert gas constituents have a cleansing effect in the plasma ambient by enhancing sputtering.

Abstract translation: 在离子注入系统中增加离子源寿命的方法使用惰性气体（例如氩或氙）引入含卤素源气体中。 惰性气体组分通过增强溅射在等离子体环境中具有清洁效果。

公开(公告)号：US06514833B1

公开(公告)日：2003-02-04

申请号：US09667600

申请日：2000-09-22

Applicant: Emi Ishida ,  Che-Hoo Ng

Inventor： Emi Ishida ,  Che-Hoo Ng

IPC: H01L2176

CPC classification number: H01L21/76237 ,  H01L21/823878

Abstract: Semiconductor devices comprising a plurality of active device regions formed in a common semiconductor substrate, e.g., CMOS devices, are formed by utilizing shallow trench isolation (STI) technology enhanced by selectively implanting the bottom surface of the trench with dopant diffusion inhibiting ions prior to filling the trench with a dielectric material and formation of opposite conductivity type well regions on either side of the trench. The inventive methodology effectively reduces or substantially eliminates deleterious counterdoping of the subsequently formed well regions resulting from thermally-induced lateral inter-diffusion of p-type and/or n-type dopant impurities used for forming the well regions.

Abstract translation: 通过利用浅沟槽隔离（STI）技术形成包括形成在公共半导体衬底（例如CMOS器件）中的多个有源器件区域的半导体器件，所述浅沟槽隔离（STI）技术通过在填充之前通过选择性地注入掺杂剂扩散抑制离子的沟槽的底表面来增强 所述沟槽具有电介质材料，并且在沟槽的任一侧上形成相反导电类型的阱区。 本发明的方法有效地减少或基本上消除了由用于形成阱区的p型和/或n型掺杂剂杂质的热诱导的横向相互扩散而导致的随后形成的阱区的有害的反掺杂。

公开(公告)号：US06372582B1

公开(公告)日：2002-04-16

申请号：US09639794

申请日：2000-08-17

Applicant: Richard P. Rouse ,  Ming Yin Hao ,  Emi Ishida ,  Effiong Ibok

Inventor： Richard P. Rouse ,  Ming Yin Hao ,  Emi Ishida ,  Effiong Ibok

IPC: H01L21336

CPC classification number: H01L29/105 ,  H01L21/223 ,  H01L21/26513

Abstract: Submicron-dimensioned, silicon-based MOS-type transistor devices having reduced tendency for “latch up” are formed by removing residual indium dopant utilized for forming a retrograde-shaped indium doping concentration profile of the channel region from the surface and uppermost stratum of the silicon substrate by a rapid thermal annealing process prior to silicon oxide thin gate insulator formation. The inventive methodology substantially eliminates deleterious indium contamination of the gate insulator layer.

Abstract translation: 通过去除用于形成沟道区域的逆向形状的铟掺杂浓度分布的残留铟掺杂物，形成具有降低的“闭锁”趋势的亚微米尺寸的硅基MOS型晶体管器件， 硅衬底通过在氧化硅薄栅极绝缘体形成之前的快速热退火工艺。 本发明的方法基本上消除了栅极绝缘体层的有害的铟污染。

公开(公告)号：US06342423B1

公开(公告)日：2002-01-29

申请号：US09667781

申请日：2000-09-22

Applicant: Emi Ishida ,  Srinath Krishnan ,  Ming Yin Hao ,  Effiong Ibok

Inventor： Emi Ishida ,  Srinath Krishnan ,  Ming Yin Hao ,  Effiong Ibok

IPC: H01L218238

CPC classification number: H01L29/6653 ,  H01L21/823468 ,  H01L21/8238 ,  H01L29/6659 ,  H01L29/7833

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of heavily-sloped source/drain junction regions but prior to annealing of the implant for dopant diffusion/activation and lattice damage relaxation. Lightly-or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract translation: 亚微米尺寸的MOS和/或CMOS晶体管通过采用由诸如UV氮化物的材料制成的可移除的侧壁间隔的工艺制造，其易于以其沉积的未增稠的状态蚀刻，但在其热 退火，致密化状态。 通过在植入重度倾斜的源极/漏极结区域之后但是在用于掺杂剂扩散/激活和晶格损伤弛豫的植入物退火之前通过用稀的HF水溶液来蚀刻沉积的未增强的间隔物。 轻微或中度掺杂的浅深度源极/漏极延伸部分在移除间隔物之后被植入和退火。