公开(公告)号：US07989864B2

公开(公告)日：2011-08-02

申请号：US12538779

申请日：2009-08-10

Applicant: Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall ,  Shenline Chen ,  Er-Xuan Ping

Inventor： Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall ,  Shenline Chen ,  Er-Xuan Ping

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L28/82 ,  H01L28/84

Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

Abstract translation: 讨论了制造半导体结构的结构和方法。 半导体结构包括具有由未掺杂硅膜形成的突起的粗糙表面。 如果半导体结构是电容器，则突起有助于增加电容器的电容。 半导体结构还包括与粗糙表面邻接的相对光滑的表面，其中相对光滑的表面由多晶材料形成。

公开(公告)号：US07868369B2

公开(公告)日：2011-01-11

申请号：US12276152

申请日：2008-11-21

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L27/108

CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

公开(公告)号：US07573121B2

公开(公告)日：2009-08-11

申请号：US11514694

申请日：2006-08-31

Applicant: Donald L Yates ,  Garry A Mercaldi ,  James J Hofmann

Inventor： Donald L Yates ,  Garry A Mercaldi ,  James J Hofmann

IPC: H01L29/94

CPC classification number: H01L27/1085 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/82 ,  H01L28/84 ,  H01L28/91

Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface. In another embodiment of a method of forming the lower electrode, the texturizing underlayer is formed by depositing overlying first and second conductive metal layers and annealing the metal layers to form surface dislocations, preferably structured as a periodic network. A conductive metal is then deposited in gaseous phase, and agglomerates onto the surface dislocations of the texturizing layer, forming nanostructures in the form of island clusters. The capacitor is completed by depositing a dielectric layer over the formed lower electrode, and forming an upper capacitor electrode over the dielectric layer. The capacitors are particularly useful in fabricating DRAM cells.

Abstract translation: 提供了形成半导体电路中的电容器的下电极的方法以及通过这些方法形成的电容器。 下电极通过形成纹理化的底层然后在其上沉积导电材料来制造。 在形成下电极的方法的一个实施方案中，通过在容器的绝缘层上沉积包含烃嵌段和含硅嵌段的聚合材料，然后随后将聚合物膜转化为浮雕而形成该组织化层 或通过暴露于UV辐射和臭氧的多孔纳米结构，导致织构化的多孔或缓蚀硅碳化硅膜。 然后将导电材料沉积在纹理化层上，导致下部电极具有上部粗糙表面。 在形成下电极的方法的另一实施例中，通过沉积覆盖的第一和第二导电金属层并退火金属层形成优选构造为周期性网络的表面位错来形成纹理化下层。 然后将导电金属沉积在气相中，并且聚集到构造层的表面位错上，形成岛簇形式的纳米结构。 电容器通过在形成的下电极上沉积介电层并在电介质层上形成上电容器电极来完成。 电容器在制造DRAM单元时特别有用。

公开(公告)号：US07192888B1

公开(公告)日：2007-03-20

申请号：US09643004

申请日：2000-08-21

Applicant: Garry A. Mercaldi

Inventor： Garry A. Mercaldi

IPC: H01L21/31

CPC classification number: H01L21/02271 ,  C23C16/0272 ,  C23C16/45525 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/0228 ,  H01L21/3185 ,  H01L28/84 ,  H01L28/91

Abstract: A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the first substance. The chemisorption product of the first and second substance may include silicon and nitrogen. The nucleation layer may comprise silicon nitride. Further, a deposition method may include forming a first part of a nucleation layer on a first surface of a substrate and forming a second part of a nucleation layer on a second surface of the substrate. A deposition layer may be formed on the first and second parts of the nucleation layer substantially non-selectively on the first part of the nucleation layer compared to the second part. The first surface may be a surface of a borophosphosilicate glass layer. The second surface may be a surface of a rugged polysilicon layer. The first and second part of the nucleation layer may be formed simultaneously.

Abstract translation: 沉积方法包括在基底上形成成核层，在成核层上形成化学吸附的至少一层单层的第一物质层，以及在第一物质上形成化学吸附的至少一层单层的第二物质层。 第一和第二物质的化学吸附产物可以包括硅和氮。 成核层可以包括氮化硅。 此外，沉积方法可以包括在基板的第一表面上形成成核层的第一部分，并在基板的第二表面上形成成核层的第二部分。 与第二部分相比，可以在成核层的第一部分上基本上非选择性地在成核层的第一和第二部分上形成沉积层。 第一表面可以是硼磷硅酸盐玻璃层的表面。 第二表面可以是坚固的多晶硅层的表面。 成核层的第一和第二部分可以同时形成。

公开(公告)号：US07087490B2

公开(公告)日：2006-08-08

申请号：US10931581

申请日：2004-08-31

Applicant: Michael Nuttall ,  Garry A. Mercaldi

Inventor： Michael Nuttall ,  Garry A. Mercaldi

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  Y10S438/954

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

公开(公告)号：US07015529B2

公开(公告)日：2006-03-21

申请号：US10453229

申请日：2003-06-03

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L29/78

CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

公开(公告)号：US06479854B1

公开(公告)日：2002-11-12

申请号：US09353574

申请日：1999-07-15

Applicant: Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

Inventor： Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

IPC: H01L27108

CPC classification number: G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L28/60

Abstract: A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier materials.

公开(公告)号：US06358793B1

公开(公告)日：2002-03-19

申请号：US09258471

申请日：1999-02-26

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L218242

CPC classification number: H01L28/92 ,  G03F7/0035 ,  G03F7/201 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0275 ,  H01L21/32139 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/91

Abstract: Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract translation: 用于集成电路的容器结构及其制造方法，而不使用机械平面化（例如化学机械平面化（CMP）），从而消除了CMP引起的缺陷和变化。 该方法利用在非机械去除暴露的表面层期间的孔的局部掩蔽来保护孔的内部。 通过将抗蚀剂层与电磁或热能的差分曝光来实现局部掩蔽。 容器结构适用于并入这种存储单元的存储器单元和装置以及其它集成电路。

公开(公告)号：US06225157B1

公开(公告)日：2001-05-01

申请号：US09260995

申请日：1999-03-01

Applicant: Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

Inventor： Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

IPC: H01L2170

CPC classification number: G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L28/60

Abstract: A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier materials.

Abstract translation: 半导体结构包括具有第一和第二相对侧的电介质层。 导电层与电介质层的第一侧相邻并且耦合到第一端子，并且导电阻挡层与电介质层的第二侧相邻并耦合到第二端子。 导电阻挡层可以由氮化钨，氮化钨，氮化钛或其它阻挡材料形成。

公开(公告)号：US20090294819A1

公开(公告)日：2009-12-03

申请号：US12538779

申请日：2009-08-10

Applicant: Randhir P.S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall ,  Shenlin Chen ,  Er-Xuan Ping

Inventor： Randhir P.S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall ,  Shenlin Chen ,  Er-Xuan Ping

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/92 ,  H01L29/02

CPC classification number: G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L28/82 ,  H01L28/84

Abstract: Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.

Abstract translation: 讨论了制造半导体结构的结构和方法。 半导体结构包括具有由未掺杂硅膜形成的突起的粗糙表面。 如果半导体结构是电容器，则突起有助于增加电容器的电容。 半导体结构还包括与粗糙表面邻接的相对光滑的表面，其中相对光滑的表面由多晶材料形成。