公开(公告)号：US4924439A

公开(公告)日：1990-05-08

申请号：US358262

申请日：1989-05-30

申请人： Katsumi Ogiue ,  Yukio Suzuki ,  Ikuro Masuda ,  Masanori Odaka ,  Hideaki Uchida

发明人： Katsumi Ogiue ,  Yukio Suzuki ,  Ikuro Masuda ,  Masanori Odaka ,  Hideaki Uchida

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/34 ,  G11C11/414 ,  G11C11/417 ,  H03K19/0944

CPC分类号： G11C7/1057 ,  G11C7/00 ,  G11C7/062 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  H03K19/09448

摘要： In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

公开(公告)号：US4868626A

公开(公告)日：1989-09-19

申请号：US044202

申请日：1987-04-30

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L29/73 ,  H01L29/732

CPC分类号： H01L27/0623 ,  Y10S257/903

摘要： A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

摘要翻译： 半导体器件有助于保持公共源极（Vcc）线的接触部分和相应晶体管的本征收集器工作区域之间的所有寄生电阻值足够小以使其不超过预定值并且几乎相同。 通过在半导体衬底中设置有预定间隔的各个晶体管的基底杂质引入层之间设置集电极连接层，使寄生电阻值变得小而几乎相同。 由于这样的结构使电阻最小化和均衡，所以抑制了施加到各个晶体管的寄生电阻产生的电压降，使其低于或基本上不超过寄生晶体管的工作阈值电压。

公开(公告)号：US4829479A

公开(公告)日：1989-05-09

申请号：US108623

申请日：1987-10-15

申请人： Kinya Mitsumoto ,  Shinji Nakazato ,  Yoshiaki Yazawa ,  Masanori Odaka ,  Hideaki Uchida ,  Nobuaki Miyakawa

发明人： Kinya Mitsumoto ,  Shinji Nakazato ,  Yoshiaki Yazawa ,  Masanori Odaka ,  Hideaki Uchida ,  Nobuaki Miyakawa

IPC分类号： G11C11/417 ,  G11C7/10

CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051

摘要： A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

摘要翻译： 一种存储器件，其中使用多个阻抗元件分压由最高工作电压下降固定电压的电压，并且公共数据线被分压电压偏置。 由于施加了来自最高工作电位的固定电压降低的电压，即使当阻抗元件的电阻值降低时，流过阻抗元件路径的电流也不会显着增加，并且获得低功耗 。 由于阻抗元件的电阻值降低，所以由寄生于公共数据线的电阻和杂散电容确定的时间常数减小。 因此，与存储在存储单元中的信息对应地产生的公用数据线的电位变化加快，数据检测时间缩短，可以缩短访问时间。

公开(公告)号：US4682200A

公开(公告)日：1987-07-21

申请号：US851485

申请日：1986-04-14

申请人： Hideaki Uchida ,  Kinya Mitsumoto ,  Yoshiaki Yazawa ,  Shinji Nakazato ,  Masanori Odaka

发明人： Hideaki Uchida ,  Kinya Mitsumoto ,  Yoshiaki Yazawa ,  Shinji Nakazato ,  Masanori Odaka

IPC分类号： H01L21/8238 ,  G11C11/34 ,  G11C11/419 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/02

CPC分类号： G11C11/419 ,  H01L27/11

摘要： A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.P) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.

摘要翻译： 一种半导体存储器件，其中在互补数据线对D，＆amp; D和D中的串联插入的等效串联电阻在各个互补数据线D，＆amp; L和D之间彼此基本相同。等效串联电阻包括 上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。 维持上拉MISFET（＆upbar＆Qp，＆upbar＆QP）和互补数据线D，＆upbar和D上存在的列切换MISFET（Qy，Qy）的奇偶校验。为了保持这个奇偶校验，形成了两个MISFET 具有相同的形状。 此外，设置与晶体管的接触的布置，使得电流流动的方向和电流路径的长度也相同。 换句话说，铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。

公开(公告)号：US4672416A

公开(公告)日：1987-06-09

申请号：US843614

申请日：1986-03-25

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L29/73 ,  H01L29/732 ,  H01L27/02

CPC分类号： H01L27/0623 ,  Y10S257/903

摘要： A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

摘要翻译： 半导体器件有助于保持公共源极（Vcc）线的接触部分和相应晶体管的本征收集器工作区域之间的所有寄生电阻值足够小以使其不超过预定值并且几乎相同。 通过在半导体衬底中设置有预定间隔的各个晶体管的基底杂质引入层之间设置集电极连接层，使寄生电阻值变得小而几乎相同。 由于这样的结构使电阻最小化和均衡，所以抑制了施加到各个晶体管的寄生电阻产生的电压降，使其低于或基本上不超过寄生晶体管的工作阈值电压。

公开(公告)号：US20100247500A1

公开(公告)日：2010-09-30

申请号：US12741340

申请日：2008-11-18

申请人： Kakuhei Isawa ,  Hideaki Uchida ,  Keisuke Furuichi ,  Fuyuko Yamamoto

发明人： Kakuhei Isawa ,  Hideaki Uchida ,  Keisuke Furuichi ,  Fuyuko Yamamoto

IPC分类号： A61K35/74 ,  C07C61/29 ,  C12N1/38 ,  A61P37/02 ,  A61P1/00

CPC分类号： A23C9/1216 ,  A23C9/127 ,  A23L33/135 ,  C12P1/04 ,  C12R1/01

摘要： The survival of lactic acid bacterial strains such as probiotic bacteria contained in yogurt etc. is improved. A lactic acid bacterium survival improver including a propionic acid bacterium fermentation product to improve the survival of a lactic acid bacterium. The propionic acid bacterium is a bacterium belonging to the genus Propionibacterium. The bacterium belonging to the genus Propionibacterium is Propionibacterium freudenreichii.

摘要翻译： 乳酸菌菌株如酸奶等中含有的益生菌的存活率提高。 一种乳酸菌存活改良剂，包括丙酸细菌发酵产物，以改善乳酸菌的存活率。 丙酸细菌是属于丙酸杆菌属的细菌。 属于丙酸杆菌属的细菌是弗氏弗氏杆菌（Propionibacterium freudenreichii）。

公开(公告)号：US20080160565A1

公开(公告)日：2008-07-03

申请号：US11720462

申请日：2005-12-01

申请人： Tadao Saito ,  Yasushi Kawai ,  Hideaki Uchida ,  Katsunori Kimura ,  Kakuhei Isawa ,  Keisuke Furuichi

发明人： Tadao Saito ,  Yasushi Kawai ,  Hideaki Uchida ,  Katsunori Kimura ,  Kakuhei Isawa ,  Keisuke Furuichi

IPC分类号： C12N1/20 ,  C12Q1/02 ,  A23L2/52 ,  A23C9/123

CPC分类号： A23C9/1234 ,  A23Y2220/37 ,  C12Q1/04 ,  G01N33/54373 ,  G01N33/56911 ,  G01N33/80 ,  G01N2333/335

摘要： Lactobacillus screening methods were carried out using surface plasmon resonance spectrums and human intestinal mucin and blood group antigens as probes. A trial to set selection criteria in the above-mentioned methods of screening for lactobacilli was made to adapt the methods to mass screening, and it was discovered that lactobacilli compatible with ABO blood groups can be screened by setting 100 RU as a criterion for judging bacterial binding under certain conditions. Using 238 lactobacillus strains, the above-mentioned screening methods and tests to judge their compatibility for the use of yogurt production were carried out, to at long last specifically discover bacillus strains compatible with blood groups A, B, and O.

摘要翻译： 使用表面等离子体共振光谱和人肠粘蛋白和血型抗原作为探针进行乳杆菌筛选方法。 对上述筛选乳酸杆菌的方法设定选择标准的试验进行了适应性筛选的方法，发现与ABO血型相容的乳杆菌可以通过设定100RU作为判断细菌的标准进行筛选 在某些条件下结合。 使用238种乳酸杆菌菌株，进行上述筛选方法和测试来判断其与酸奶生产的相容性，最后特别发现与血型A，B和O相容的芽孢杆菌菌株。

公开(公告)号：US20070137525A1

公开(公告)日：2007-06-21

申请号：US11649289

申请日：2007-01-04

申请人： Hiroshi Kokuta ,  Katsuhiro Kokuta ,  Hideaki Uchida ,  Kenji Kokuta ,  Naoto Kokuta

发明人： Hiroshi Kokuta ,  Katsuhiro Kokuta ,  Hideaki Uchida ,  Kenji Kokuta ,  Naoto Kokuta

IPC分类号： C09D1/00 ,  C09D5/20 ,  C04B40/00

CPC分类号： C09K21/14 ,  C04B28/006 ,  C04B28/04 ,  C04B28/06 ,  C04B28/26 ,  C04B40/0039 ,  C04B2103/10 ,  C04B2111/28 ,  C09K21/02 ,  Y02P40/165 ,  C04B22/0013 ,  C04B22/10 ,  C04B22/126 ,  C04B22/165 ,  C04B40/0263 ,  C04B24/02 ,  C04B24/282 ,  C04B38/02 ,  C04B40/0218 ,  C04B2103/63

摘要： A water-soluble inorganic composition obtained by reacting an inorganic dissolution promoter with at least one solute selected from the group consisting of metal silicon, boric acid, and borax at a ratio of the inorganic dissolution promoter to the solute of 1:10 to 1:100 by weight, wherein the inorganic dissolution promoter is obtained by mixing in water (A) at least one compound selected from the group consisting of an alkali metal fluoride, an alkali metal phosphite, an alkali metal sulfite, an Alkali metal nitrite, sulfurous acid, nitrous acid, and phosphorous acid, alkali metal phosphate, alkali metal nitrate, alkali metal sulfate, phosphoric acid, nitric acid, sulfuric acid and (B) at least one alkali metal hydroxide at a ratio of (A):(B) of 1:9 to 4:1 by weight; a plasticized substance; and a foamed inorganic substance are provided. According to the present invention, a homogeneous and high concentration aqueous solution of a water-soluble inorganic composition is provided by homogeneously dissolving water-insoluble metal silicon or a scarcely water-soluble inorganic boron compound in water in an excess amount without causing these inorganic materials to remain at the bottom of the reactor, and a plasticized substance and foamed inorganic substance excelling in processability and handling properties and useful as a civil engineering and construction material are also provided.

摘要翻译： 将无机溶解促进剂与选自金属硅，硼酸和硼砂中的至少一种溶质以无机溶解促进剂与溶质的比例为1:10至1：1的反应获得的水溶性无机组合物， 100重量份，其中无机溶解促进剂通过在水（A）中混合至少一种选自碱金属氟化物，碱金属亚磷酸盐，碱金属亚硫酸盐，碱金属亚硝酸盐，亚硫酸 ，亚硝酸和亚磷酸，碱金属磷酸盐，碱金属硝酸盐，碱金属硫酸盐，磷酸，硝酸，硫酸和（B）至少一种碱金属氢氧化物，其比例为（A）：（B） 1：9至4：1; 增塑物质 并提供发泡无机物质。 根据本发明，通过将不溶于水的金属硅或几乎不溶于水的无机硼化合物在过量的水中均匀溶解而不引起这些无机材料，提供均匀且高浓度的水溶性无机组合物水溶液 保留在反应器的底部，并且还提供了可加工性和操作性优异的增塑物质和发泡无机物质，并且用作土木工程和建筑材料。

公开(公告)号：US06740958B2

公开(公告)日：2004-05-25

申请号：US10115101

申请日：2002-04-04

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L2900

CPC分类号： H01L27/0623 ,  H01L27/0214 ,  H01L27/0218 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/10805

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

公开(公告)号：US5386135A

公开(公告)日：1995-01-31

申请号：US229340

申请日：1994-04-12

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10805 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/0218 ,  H01L27/105 ,  Y10S257/901 ,  Y10S257/904

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。