公开(公告)号：US20110073928A1

公开(公告)日：2011-03-31

申请号：US12894844

申请日：2010-09-30

申请人： ByungKyu Cho ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

发明人： ByungKyu Cho ,  Sunghoi Hur ,  Jaeduk Lee ,  Jungdal Choi

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/7881

摘要： Provided are a non-volatile memory device and a method of forming the same. The non-volatile memory device includes: a tunnel insulation layer on a substrate; a floating gate on the tunnel insulation layer; a blocking insulation layer on the floating gate; a first barrier pattern, between the top of the floating gate and the blocking insulation layer, having a higher conduction band energy level than the floating gate; and a control gate on the blocking insulation layer.

摘要翻译： 提供一种非易失性存储器件及其形成方法。 非易失性存储器件包括：衬底上的隧道绝缘层; 隧道绝缘层上的浮栅; 浮栅上的阻挡绝缘层; 在浮置栅极的顶部和阻挡绝缘层之间的第一阻挡图案具有比浮动栅极更高的导带能级; 和阻挡绝缘层上的控制栅极。

公开(公告)号：US10418278B2

公开(公告)日：2019-09-17

申请号：US15857961

申请日：2017-12-29

申请人： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

发明人： Dohyun Lee ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11573 ,  H01L27/11575 ,  H01L23/528

摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

公开(公告)号：US10056404B2

公开(公告)日：2018-08-21

申请号：US14989955

申请日：2016-01-07

申请人： Jaeduk Lee ,  Youngwoo Park

发明人： Jaeduk Lee ,  Youngwoo Park

IPC分类号： H01L29/792 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/06

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11573

摘要： The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.

公开(公告)号：US20170011996A1

公开(公告)日：2017-01-12

申请号：US15201922

申请日：2016-07-05

申请人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

发明人： Dohyun LEE ,  Youngwoo Park ,  Junghoon Park ,  Jaeduk Lee

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/115

CPC分类号： H01L21/76877 ,  H01L21/76816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

摘要翻译： 半导体器件包括在半导体衬底上的半导体图案，半导体图案上的三维存储器阵列以及半导体图案和半导体衬底之间的外围互连结构。 外围互连结构包括在较低互连结构上的上互连结构。 上互连结构包括上互连和上阻挡层。 下部互连结构包括下部互连和下部阻挡层。 上阻挡层在上互连的底表面下方并且不覆盖上互连的侧表面。 下阻挡层在下互连的底表面下方并且覆盖下互连的侧表面。

公开(公告)号：US20160343450A1

公开(公告)日：2016-11-24

申请号：US15157720

申请日：2016-05-18

申请人： Changhyun LEE ,  Dohyun LEE ,  Youngwoo PARK ,  Su Jin AHN ,  Jaeduk LEE

发明人： Changhyun LEE ,  Dohyun LEE ,  Youngwoo PARK ,  Su Jin AHN ,  Jaeduk LEE

IPC分类号： G11C16/34 ,  G11C16/04 ,  H01L29/16 ,  H01L23/528 ,  H01L29/04 ,  G11C16/10 ,  H01L27/115

CPC分类号： H01L27/11524 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16

摘要： Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns. The three-dimensional semiconductor memory device further comprising a first ground selection transistor that includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor that includes a second gate pattern positioned on the first gate pattern and the first pillar, and wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.

摘要翻译： 公开了一种三维半导体存储器件，包括形成在第一衬底上的单元阵列和形成在第二衬底上的外围电路，所述外围电路至少部分地与第一衬底重叠，其中外围电路被配置为提供控制信号 单元格阵列。 电池阵列包括在第一衬底上交替堆叠的绝缘图案和栅极图案，以及至少第一柱，其沿垂直于第一衬底的方向形成，并且通过绝缘图案和栅极图案与第一衬底接触。 所述三维半导体存储器件还包括第一接地选择晶体管，其包括与所述第一衬底和所述第一柱相邻的第一栅极图案，以及第二接地选择晶体管，所述第二接地选择晶体管包括位于所述第一栅极图案上的第二栅极图案， 第一支柱，并且其中第一接地选择晶体管不可编程，并且第二接地选择晶体管是可编程的。

公开(公告)号：US09337207B2

公开(公告)日：2016-05-10

申请号：US14191542

申请日：2014-02-27

申请人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jintaek Park ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L29/76 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor memory device includes a substrate including a cell region and an interconnection region, adjacent first and second rows of vertical channels extending vertically from the substrate in the cell region, and layers of word lines stacked on the substrate. Each layer includes a first word line through which the first row of vertical channels passes and a second word line through which the second row of vertical channels passes, and the word lines include respective word line pads extending into the interconnection region. An isolation pattern separates the first and second word lines in the cell region and the interconnection region. First and second pluralities of contact plugs are disposed on opposite sides of the isolation pattern in the interconnection region and contact the word line pads.

摘要翻译： 半导体存储器件包括：衬底，其包括单元区域和互连区域;相邻的从单元区域中的衬底垂直延伸的第一和第二排垂直沟道以及堆叠在衬底上的字线层。 每层包括第一行垂直通道通过的第一字线和第二行垂直通道通过的第二字线，并且字线包括延伸到互连区域中的相应字线焊盘。 隔离图案分离单元区域和互连区域中的第一和第二字线。 第一和第二多个接触插塞设置在互连区域中的隔离图案的相对侧上，并与字线焊盘接触。

公开(公告)号：US20160005760A1

公开(公告)日：2016-01-07

申请号：US14725476

申请日：2015-05-29

申请人： Dohyun Lee ,  Jaegoo Lee ,  Young-Jin Kwon ,  Youngwoo Park ,  Jaeduk Lee

发明人： Dohyun Lee ,  Jaegoo Lee ,  Young-Jin Kwon ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L27/115 ,  H01L29/10 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/1033 ,  H01L29/7926

摘要： A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern. The upper channel structure includes a second vertical semiconductor pattern electrically connected to the first vertical semiconductor pattern with the first connecting semiconductor pattern disposed therebetween.

摘要翻译： 半导体器件包括下层堆叠结构，其包括交替重复堆叠在衬底上的下栅电极和下绝缘层。 半导体器件包括上堆叠结构，其包括交替重复堆叠在下堆叠结构上的上栅电极和上绝缘层。 下部通道结构穿透下部堆叠结构。 上通道结构穿透并连接到上堆叠结构。 下部垂直绝缘体设置在下部堆叠结构和下部通道结构之间。 下通道结构包括连接到基板的第一垂直半导体图案和布置在第一垂直半导体图案上的第一连接半导体图案。 上通道结构包括电连接到第一垂直半导体图案的第二垂直半导体图案，其间设置有第一连接半导体图案。

公开(公告)号：US09224429B2

公开(公告)日：2015-12-29

申请号：US14635588

申请日：2015-03-02

申请人： Jintaek Park ,  Kohji Kanamori ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jintaek Park ,  Kohji Kanamori ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： G11C5/02 ,  H01L27/115 ,  G11C7/02 ,  G11C7/18 ,  G11C7/10

CPC分类号： G11C5/025 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/18 ,  H01L27/11573 ,  H01L27/11582

摘要： According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.

公开(公告)号：US09019739B2

公开(公告)日：2015-04-28

申请号：US14152440

申请日：2014-01-10

申请人： Jintaek Park ,  Kohji Kanamori ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jintaek Park ,  Kohji Kanamori ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： G11C5/02 ,  H01L27/115 ,  G11C7/02 ,  G11C7/18 ,  G11C7/10

CPC分类号： G11C5/025 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/18 ,  H01L27/11573 ,  H01L27/11582

摘要： According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.

摘要翻译： 根据本发明构思的示例性实施例，三维半导体器件可以包括：存储单元阵列，其包括可以三维布置的存储器单元，所述存储单元阵列包括与右侧相对的左侧， 平面图的底面; 与存储单元阵列的左侧和右侧中的至少一个相邻的至少一个字线解码器; 邻近存储单元阵列的底侧的页缓冲器; 以及与存储单元阵列的顶侧和底侧之一相邻的串选择线解码器。

公开(公告)号：US20140197469A1

公开(公告)日：2014-07-17

申请号：US14150452

申请日：2014-01-08

申请人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

发明人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

IPC分类号： H01L27/105

CPC分类号： H01L27/1052 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556

摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

摘要翻译： 提供三维半导体器件及其操作方法。 三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。 所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。 例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。