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    Power electronic devices, methods of manufacturing the same, and integrated circuit modules including the same
    22.
    发明申请
    Power electronic devices, methods of manufacturing the same, and integrated circuit modules including the same 有权
    电力电子装置及其制造方法以及包括其的集成电路模块

    公开(公告)号：US20110068370A1

    公开(公告)日：2011-03-24

    申请号：US12923126

    申请日：2010-09-03

    Applicant: Jong-seob Kim ,  Ki-ha Hong ,  Jae-joon Oh ,  Hyuk-soon Choi ,  In-jun Whang ,  Jai-kwang Shin

    Inventor： Jong-seob Kim ,  Ki-ha Hong ,  Jae-joon Oh ,  Hyuk-soon Choi ,  In-jun Whang ,  Jai-kwang Shin

    IPC: H01L29/778 ,  H01L21/335

    CPC classification number: H01L29/207 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

    Abstract: Power electronic devices including 2-dimensional electron gas (2DEG) channels and methods of manufacturing the same. A power electronic device includes lower and upper material layers for forming a 2DEG channel, and a gate contacting an upper surface of the upper material layer. A region below the gate of the 2DEG channel is an off region where the density of a 2DEG is reduced or zero. The entire upper material layer may be continuous and may have a uniform thickness. A region of the upper material layer under the gate contains an impurity for reducing or eliminating a lattice constant difference between the lower and upper material layers.

    Abstract translation: 包括二维电子气体（2DEG）通道的电力电子装置及其制造方法。 电力电子设备包括用于形成2DEG通道的下部和上部材料层，以及与上部材料层的上表面接触的栅极。 2DEG通道的栅极下方的区域是2DEG的密度减小或为零的截止区域。 整个上部材料层可以是连续的并且可以具有均匀的厚度。 在栅极下方的上部材料层的区域包含用于减少或消除下部和上部材料层之间的晶格常数差的杂质。

    Substrate structure, semiconductor device fabricated from the same, and method of fabricating the semiconductor device
    26.
    发明授权
    Substrate structure, semiconductor device fabricated from the same, and method of fabricating the semiconductor device 有权
    基板结构，由其制造的半导体器件以及半导体器件的制造方法

    公开(公告)号：US08921890B2

    公开(公告)日：2014-12-30

    申请号：US13551217

    申请日：2012-07-17

    Applicant: Hyuk-soon Choi ,  Jong-seob Kim ,  Jai-kwang Shin ,  Chang-yong Um ,  Jae-joon Oh ,  Jong-bong Ha ,  In-jun Hwang ,  Ki-ha Hong

    Inventor： Hyuk-soon Choi ,  Jong-seob Kim ,  Jai-kwang Shin ,  Chang-yong Um ,  Jae-joon Oh ,  Jong-bong Ha ,  In-jun Hwang ,  Ki-ha Hong

    IPC: H01L31/102

    CPC classification number: H01L29/7813 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/41741 ,  H01L29/66734

    Abstract: According to example embodiments, a substrate structure may include a GaN-based third material layer, a GaN-based second material layer, a GaN-based first material layer, and a buffer layer on a non-GaN-based substrate. The GaN-based first material layer may be doped with a first conductive type impurity. The GaN-based second material layer may be doped with a second conductive type impurity at a density that is less than a density of the first conductive type impurity in the first GaN-based material layer. The GaN-based third material layer may be doped with a first conductive type impurity at a density that is less than the density of the first conductive type impurity of the GaN-based first material layer. After a second substrate is attached onto the substrate structure, the non-GaN-based substrate may be removed and a GaN-based vertical type semiconductor device may be fabricated on the second substrate.

    Abstract translation: 根据示例实施例，衬底结构可以包括GaN基第三材料层，GaN基第二材料层，GaN基第一材料层和非GaN基衬底上的缓冲层。 GaN基第一材料层可以掺杂有第一导电类型的杂质。 GaN基第二材料层可以以小于第一GaN基材料层中的第一导电类型杂质的密度的密度掺杂第二导电型杂质。 GaN基第三材料层可以以比GaN基第一材料层的第一导电类型杂质的密度小的密度掺杂第一导电型杂质。 在将第二衬底附着到衬底结构上之后，可以去除非GaN基衬底，并且可以在第二衬底上制造GaN基垂直型半导体器件。

    SUBSTRATE STRUCTURE, SEMICONDUCTOR DEVICE FABRICATED FROM THE SAME, AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE
    27.
    发明申请
    SUBSTRATE STRUCTURE, SEMICONDUCTOR DEVICE FABRICATED FROM THE SAME, AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE 有权
    衬底结构，由其制成的半导体器件以及制造半导体器件的方法

    公开(公告)号：US20130175538A1

    公开(公告)日：2013-07-11

    申请号：US13551217

    申请日：2012-07-17

    Applicant: Hyuk-soon CHOI ,  Jong-seob KIM ,  Jai-kwang SHIN ,  Chang-yong UM ,  Jae-joon OH ,  Jong-bong HA ,  In-jun HWANG ,  Ki-ha HONG

    Inventor： Hyuk-soon CHOI ,  Jong-seob KIM ,  Jai-kwang SHIN ,  Chang-yong UM ,  Jae-joon OH ,  Jong-bong HA ,  In-jun HWANG ,  Ki-ha HONG

    IPC: H01L29/20 ,  H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7813 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/41741 ,  H01L29/66734

    Abstract: According to example embodiments, a substrate structure may include a GaN-based third material layer, a GaN-based second material layer, a GaN-based first material layer, and a buffer layer on a non-GaN-based substrate. The GaN-based first material layer may be doped with a first conductive type impurity. The GaN-based second material layer may be doped with a second conductive type impurity at a density that is less than a density of the first conductive type impurity in the first GaN-based material layer. The GaN-based third material layer may be doped with a first conductive type impurity at a density that is less than the density of the first conductive type impurity of the GaN-based first material layer. After a second substrate is attached onto the substrate structure, the non-GaN-based substrate may be removed and a GaN-based vertical type semiconductor device may be fabricated on the second substrate.

    Abstract translation: 根据示例实施例，衬底结构可以包括GaN基第三材料层，GaN基第二材料层，GaN基第一材料层和非GaN基衬底上的缓冲层。 GaN基第一材料层可以掺杂有第一导电类型的杂质。 GaN基第二材料层可以以小于第一GaN基材料层中的第一导电类型杂质的密度的密度掺杂第二导电型杂质。 GaN基第三材料层可以以比GaN基第一材料层的第一导电类型杂质的密度小的密度掺杂第一导电型杂质。 在将第二衬底附着到衬底结构上之后，可以去除非GaN基衬底，并且可以在第二衬底上制造GaN基垂直型半导体器件。

    Method Of Manufacturing High Electron Mobility Transistor
    29.
    发明申请
    Method Of Manufacturing High Electron Mobility Transistor 有权
    制造高电子迁移率晶体管的方法

    公开(公告)号：US20110212582A1

    公开(公告)日：2011-09-01

    申请号：US13017361

    申请日：2011-01-31

    Applicant: Ki-ha Hong ,  U-in Chung ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang

    Inventor： Ki-ha Hong ,  U-in Chung ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang

    IPC: H01L21/335

    CPC classification number: H01L29/402 ,  H01L29/0891 ,  H01L29/66462 ,  H01L29/7786

    Abstract: A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate.

    Abstract translation: 制造高电子迁移率晶体管（HEMT）的方法可以包括在衬底上形成具有不同晶格常数的第一和第二材料层，在第二材料层上形成源极，漏极和栅极，以及改变第二材料层 在栅极和漏极之间形成不同的材料层，或改变第二材料层的厚度，或在第二材料层上形成p型半导体层。 第二材料层的变化可以在栅极和漏极之间的第二材料层的整个区域中发生，或者仅在与栅极相邻的第二材料层的部分区域中发生。 p型半导体层可以形成在栅极和漏极之间的第二材料层的整个顶表面上，或者仅形成在与栅极相邻的顶表面的部分区域上。

    Apparatus and method for generating ions of an ion implanter
    30.
    发明授权
    Apparatus and method for generating ions of an ion implanter 有权
    用于产生离子注入机离子的装置和方法

    公开(公告)号：US07476868B2

    公开(公告)日：2009-01-13

    申请号：US11453075

    申请日：2006-06-15

    Applicant: Seong Gu Kim ,  Jai Kwang Shin ,  Jae Joon Oh

    Inventor： Seong Gu Kim ,  Jai Kwang Shin ,  Jae Joon Oh

    IPC: H01J37/08 ,  H01J37/30

    CPC classification number: H01J37/08 ,  H01J27/024 ,  H01J27/08 ,  H01J37/3171

    Abstract: An ion generator of an ion implanter, the ion generator includes: an arc chamber provided with a slit for ion extraction and forming an equipotential surface with a first voltage; a filament installed inside of the arc chamber, heated to a predetermined temperature and generating electrons; magnetic field devices provided outside of the arc chamber and supplied with a current from a current source and generating a magnetic field in the arc chamber; a gas discharge device injecting a predetermined gas into the arc chamber; and an electrode positioned opposite to the slit and supplied with a second voltage having a high voltage than the first voltage from a voltage source and generating a magnetic field in the arc chamber.

    Abstract translation: 离子注入机的离子发生器，所述离子发生器包括：电弧室，设置有用于离子提取的狭缝并形成具有第一电压的等电位面; 安装在电弧室内的灯丝，加热到预定温度并产生电子; 磁场装置设置在电弧室外部，并从电流源提供电流并在电弧室中产生磁场; 将预定气体注入到电弧室中的气体放电装置; 以及电极，与所述狭缝相对设置，并且从电压源提供具有比所述第一电压高的电压的第二电压并在所述电弧室中产生磁场。

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