公开(公告)号：US20080163153A1

公开(公告)日：2008-07-03

申请号：US11619320

申请日：2007-01-03

Applicant: Maharaj Mukherjee ,  James A. Culp ,  Scott M. Mansfield

Inventor： Maharaj Mukherjee ,  James A. Culp ,  Scott M. Mansfield

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A method, system and computer program product for verifying printability of a mask layout for a photolithographic process are disclosed. A simulation of the photolithographic process for the designed mask layout is simulated using a simplified version of the mask layout with a lower accuracy to generate a lower accuracy simulated image. Where the lower accuracy simulated image is determined as potentially including an error, a further simulation of the designated portion of the mask layout with a higher accuracy will be performed.

Abstract translation: 公开了一种用于验证光刻工艺的掩模布局的可印刷性的方法，系统和计算机程序产品。 使用精度较低的掩模布局的简化版本来模拟设计的掩模布局的光刻工艺的模拟，以产生较低精度的模拟图像。 在将低精度模拟图像确定为潜在地包括错误的情况下，将执行具有更高精度的掩模布局的指定部分的进一步模拟。

公开(公告)号：US08458625B2

公开(公告)日：2013-06-04

申请号：US13193716

申请日：2011-07-29

Applicant: Pavan Y. Bashaboina ,  James A. Culp

Inventor： Pavan Y. Bashaboina ,  James A. Culp

IPC: G06F17/50

CPC classification number: G03F7/70433 ,  G03F7/705

Abstract: Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization.

Abstract translation: 与光刻层相关的潜在平版印刷热点由识别标记区域的标记层标记。 为每个标记区域中的光刻级别中的每个设计形状生成多重层。 每个多重层包括在光刻层级中的每个设计形状的不同类型的变体。 不同类型的变体对应于不同的设计环境。 在长距离效应的约束下，每种类型的变体进行平版印刷模拟，例如由光刻层面中的相邻形状提供的图案密度。 在每个标记区域中，评估光刻模拟的结果以确定变体中的最佳类型。 为每个标记区域中的光刻级别保留最佳类型，从而提供芯片设计布局，其中各种标记区域可以包括不同类型的变体形状以提供局部光刻优化。

公开(公告)号：US08429576B2

公开(公告)日：2013-04-23

申请号：US13471789

申请日：2012-05-15

Applicant: James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

Inventor： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

IPC: G06F17/50

CPC classification number: G01R31/26 ,  G06F17/5045

Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

公开(公告)号：US20130031519A1

公开(公告)日：2013-01-31

申请号：US13193716

申请日：2011-07-29

Applicant: Pavan Y. Bashaboina ,  James A. Culp

Inventor： Pavan Y. Bashaboina ,  James A. Culp

IPC: G06F17/50

CPC classification number: G03F7/70433 ,  G03F7/705

Abstract: Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization.

Abstract translation: 与光刻层相关的潜在平版印刷热点由识别标记区域的标记层标记。 为每个标记区域中的光刻级别中的每个设计形状生成多重层。 每个多重层包括在光刻层级中的每个设计形状的不同类型的变体。 不同类型的变体对应于不同的设计环境。 在长距离效应的约束下，每种类型的变体进行平版印刷模拟，例如由光刻层面中的相邻形状提供的图案密度。 在每个标记区域中，评估光刻模拟的结果以确定变体中的最佳类型。 为每个标记区域中的光刻级别保留最佳类型，从而提供芯片设计布局，其中各种标记区域可以包括不同类型的变体形状以提供局部光刻优化。

公开(公告)号：US08302068B2

公开(公告)日：2012-10-30

申请号：US12689481

申请日：2010-01-19

Applicant: James A. Culp ,  Lars W. Liebmann

Inventor： James A. Culp ,  Lars W. Liebmann

IPC: G06F15/04 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: The present invention provides a method and computer program product for designing an on-wafer target for use by a model-based design tool such as OPC or OPC verification. The on-wafer target is modified by modifying a critical dimension so as to improve or optimize an electrical characteristic, while also ensuring that one or more yield constraints are satisfied. The use of an electrically optimized target can result in cost-effective mask designs that better meet the designers' intent.

Abstract translation: 本发明提供了一种用于设计用于由基于模型的设计工具（例如OPC或OPC验证）使用的晶圆上目标的方法和计算机程序产品。 通过修改关键尺寸来修改晶圆上目标，以改善或优化电特性，同时还确保满足一个或多个屈服约束。 使用电气优化的目标可以产生更符合设计者意图的经济高效的面罩设计。

公开(公告)号：US08232215B2

公开(公告)日：2012-07-31

申请号：US12622557

申请日：2009-11-20

Applicant: James A. Culp ,  Jeffrey P. Gambino ,  John J. Ellis-Monaghan ,  Kirk D. Peterson ,  Jed H. Rankin

Inventor： James A. Culp ,  Jeffrey P. Gambino ,  John J. Ellis-Monaghan ,  Kirk D. Peterson ,  Jed H. Rankin

IPC: H01L21/302

CPC classification number: H01L21/31144

Abstract: A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.

Abstract translation: 用于形成邻接多个均匀间隔的地形特征的多个可变线宽间隔物的方法在位于多个均匀间隔的地形特征之上的间隔物材料层上使用共形抗蚀剂层。 保形抗蚀剂层被差异地曝光和显影以提供在形成可变线宽间隔物时用作牺牲掩模的差分厚度抗蚀剂层。 用于形成均匀线宽间隔物的方法，其邻接狭窄间隔的地形特征和在相同基底上的宽间隔的地形特征，使用可变厚度间隔物材料层的掩蔽各向同性蚀刻，以提供更均匀的部分蚀刻的间隔物材料层，随后是未掩模的各向异性蚀刻 的部分蚀刻的间隔材料层。 用于形成均匀线宽间隔物的相关方法使用包括至少一个掩模处理步骤的两步各向异性蚀刻方法。

公开(公告)号：US20120167029A1

公开(公告)日：2012-06-28

申请号：US13413759

申请日：2012-03-07

Applicant: John M. Cohn ,  James A. Culp ,  Ulrich A. Finkler ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin Fuw Lee ,  Lars W. Liebmann ,  Gregory A. Northrop ,  Nakgeuon Seong ,  Rama N. Singh ,  Leon Stok ,  Pieter J. Woltgens

Inventor： John M. Cohn ,  James A. Culp ,  Ulrich A. Finkler ,  Fook-Luen Heng ,  Mark A. Lavin ,  Jin Fuw Lee ,  Lars W. Liebmann ,  Gregory A. Northrop ,  Nakgeuon Seong ,  Rama N. Singh ,  Leon Stok ,  Pieter J. Woltgens

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5072

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract translation: 一种用于设计复杂集成电路（IC）的设计系统，一种IC设计方法和程序产品。 布局单元接收表示网格和字形格式的部分的电路描述。 检查单元检查设计的网格和字形部分。 精心设计单元从检查的设计生成目标布局。 数据准备单元准备掩模制作的目标布局。 模式高速缓存单元用先前缓存的结果有选择地替换设计的部分，以提高设计效率。

公开(公告)号：US20120149200A1

公开(公告)日：2012-06-14

申请号：US12966432

申请日：2010-12-13

Applicant: James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Christa R. Willets

Inventor： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Christa R. Willets

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/28035 ,  H01L21/76237 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/78

Abstract: A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.

Abstract translation: 一种形成电介质间隔物的方法，包括提供包括具有第一多个栅极结构的第一区域和具有第二多个栅极结构的第二区域和至少一种含氧化物的材料或含碳材料的衬底。 在第一区域上形成厚度小于存在于第二区域中的含氮化物层的厚度的含氮化物层。 在第一多个第二多个栅极结构上从氮化物含有层形成电介质间隔物。 所述至少一种含氧化物的材料或含碳材料加速了第二区域中的蚀刻，使得第一区域中的电介质间隔物的厚度基本上等于衬底的第二区域中的电介质间隔物的厚度。

公开(公告)号：US08176444B2

公开(公告)日：2012-05-08

申请号：US12426475

申请日：2009-04-20

Applicant: Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

Inventor： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/10

Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

Abstract translation: 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

公开(公告)号：US07865864B2

公开(公告)日：2011-01-04

申请号：US12024188

申请日：2008-02-01

Applicant: Shayak Banerjee ,  James A. Culp ,  Praveen Elakkumanan ,  Lars W. Liebmann

Inventor： Shayak Banerjee ,  James A. Culp ,  Praveen Elakkumanan ,  Lars W. Liebmann

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic.

Abstract translation: 描述了提供电驱动光学邻近校正的方法。 在一个实施例中，存在执行电驱动光学邻近校正的方法。 在本实施例中，接收表示由特征和边缘定义的多个分层形状的集成电路掩模布局。 在掩模布局上运行光刻仿真。 从掩模布局的每层的光刻模拟的输出中提取电特性。 确定提取的电特性是否与目标电特性一致。 响应于确定提取的掩模布局中的层的电特性不符合目标电特性，调整掩模布局中的多个分层形状的边缘。