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    SEMICONDUCTOR DEVICE INCLUDING GROUP III-V COMPOUND SEMICONDUCTOR LAYER, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
    21.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING GROUP III-V COMPOUND SEMICONDUCTOR LAYER, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 审中-公开
    包括III-V族化合物半导体层的半导体器件及制造半导体器件的方法

    公开(公告)号：US20130105946A1

    公开(公告)日：2013-05-02

    申请号：US13593210

    申请日：2012-08-23

    Applicant: Sang-moon LEE ,  Jai-kwang SHIN ,  Young-jin CHO

    Inventor： Sang-moon LEE ,  Jai-kwang SHIN ,  Young-jin CHO

    IPC: H01L29/20 ,  H01L21/20

    CPC classification number: H01L21/02381 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/785 ,  Y02E10/544 ,  Y02P70/521

    Abstract: A semiconductor device may include a silicon (Si) substrate including a hole, a hard mask around the hole on the Si substrate, a first material layer filling the hole and on a portion of the hard mask, an upper material layer on the first material layer, and a device layer on the upper material layer. The first material layer may be a Group III-V material layer. The Group III-V material layer may be a Group III-V compound semiconductor layer. The upper material layer may be a portion of the first material layer. The upper material layer may include one of a same material as the first material layer and a different material from the first material layer.

    Abstract translation: 半导体器件可以包括包括孔的硅（Si）衬底，围绕Si衬底上的孔的硬掩模，填充该孔的第一材料层和硬掩模的一部分上的第一材料层，第一材料上的上部材料层 层和上层材料层上的器件层。 第一材料层可以是III-V族材料层。 III-V族材料层可以是III-V族化合物半导体层。 上部材料层可以是第一材料层的一部分。 上部材料层可以包括与第一材料层相同的材料和与第一材料层不同的材料之一。

    Substrate manufacturing method for sensor applications using optical characteristics and the substrate therefrom
    24.
    发明授权
    Substrate manufacturing method for sensor applications using optical characteristics and the substrate therefrom 有权
    使用光学特性的传感器应用的基板制造方法及其基板

    公开(公告)号：US08414965B2

    公开(公告)日：2013-04-09

    申请号：US12741389

    申请日：2008-10-23

    Applicant: Yong Jin Cho ,  Chul Jin Kim ,  Chong Tai Kim ,  Sung Wook Choi ,  Jae Ho Kim ,  Hyo Sop Kim ,  Jin Ho Kim

    Inventor： Yong Jin Cho ,  Chul Jin Kim ,  Chong Tai Kim ,  Sung Wook Choi ,  Jae Ho Kim ,  Hyo Sop Kim ,  Jin Ho Kim

    IPC: B05D5/12 ,  C23C14/28 ,  C23C14/30 ,  C23C14/14 ,  H05B6/00 ,  H05B7/00 ,  B05D1/18 ,  B05D3/00

    CPC classification number: G01N21/658 ,  G01N21/554 ,  Y10T428/24372 ,  Y10T428/31678

    Abstract: A method for manufacturing a substrate of an analytical sensor and the substrate thus prepared are disclosed. The method for manufacturing the substrate of the sensor application according to the present invention is characterized in that it comprises (a) the step of preparing a dispersed solution of nanoparticles, which are stable in a volatile organic solvent due to surface modification of nanoparticles having a pre-designed certain size on the nanometer level with an organic functional group (b) the step of preparing a single layer film of nanoparticles surface-modified with the organic functional group on the interface using said dispersed solution of nanoparticles on the basis of the Langmuir-Blodgett method, and then transferring said single layer film of nanoparticles to the substrate; and (c) the step of coating the substrate to which said single layer film of nanoparticles is transferred, with the metal thin film by means of the vacuum vapor deposition, and then optionally removing nanoparticles to manufacture a nanostructure to be used as the analytical sensor using optical characteristics. According to the method for manufacturing the substrate of the sensor application according to the present invention as above, the nanoparticles can be uniformly fixed on the solid substrate having a great area above 10×10 cm2 using the Langmuir-Blodgett method, and by such method the size, distance and shape of nanoparticles can be controlled to manufacture the nanostructures to be used as the analytical sensor, which is possible to reproduce and mass-produce. When the sensitivity property of the sensor is measured using the nanostructure substrate, thus produced, to be used as the analytical sensor, it can be identified that the sensitivity can be highly improved.

    Abstract translation: 公开了一种用于制造如此制备的分析传感器和衬底的衬底的方法。 根据本发明的传感器应用的基板的制造方法的特征在于，其包括（a）制备纳米颗粒的分散溶液的步骤，所述分散溶液由于纳米颗粒的表面改性而在挥发性有机溶剂中稳定， 用有机官能团预先设计在纳米级上的一定尺寸（b）制备在界面上用有机官能团表面改性的纳米颗粒单层薄膜的步骤，该纳米粒子基于Langmuir -Blodgett方法，然后将所述单层纳米颗粒膜转移到基底; 和（c）通过真空气相沉积用金属薄膜涂覆纳米颗粒的单层膜转移到其上的基底的步骤，然后任选地除去纳米颗粒以制造用作分析传感器的纳米结构 使用光学特性。 根据如上所述的根据本发明的传感器应用的基板的制造方法，可以使用Langmuir-Blodgett方法将纳米颗粒均匀地固定在具有大于10×10cm 2的大面积的固体基板上，并且通过这种方法 可以控制纳米颗粒的尺寸，距离和形状，以制造用作分析传感器的纳米结构，其可以再现和批量生产。 当使用由此产生的纳米结构基板测量传感器的灵敏度特性作为分析传感器时，可以确定可以高度提高灵敏度。

    CAPACITOR-FREE LOW DROP-OUT REGULATOR
    25.
    发明申请
    CAPACITOR-FREE LOW DROP-OUT REGULATOR 审中-公开
    无电容低压降稳压器

    公开(公告)号：US20130082672A1

    公开(公告)日：2013-04-04

    申请号：US13348464

    申请日：2012-01-11

    Applicant: Myeung Su KIM ,  Joon Hyung LIM ,  Sang Hoon HWANG ,  Sang Hyun MIN ,  Han Jin CHO ,  Tah Joon PARK

    Inventor： Myeung Su KIM ,  Joon Hyung LIM ,  Sang Hoon HWANG ,  Sang Hyun MIN ,  Han Jin CHO ,  Tah Joon PARK

    IPC: G05F1/10

    CPC classification number: G05F1/575

    Abstract: There is provided a low drop-out regulator. The low drop-out regulator includes an amplifier including an odd number of operational amplifiers connected to one another in series, and an output unit including a pass transistor operated by an output from the amplifier and generating an output voltage to be applied to a load, wherein the pass transistor is an N-channel transistor, and the amplifier controls a feedback loop gain between an output terminal of one of the odd number of operational amplifiers and the output unit. The feedback loop gain may be controlled independently from the trans-conductance of the pass transistor, whereby the stable output voltage may be generated, even in the case that the load and the input voltage are changed, and the design parameter may be simplified.

    Abstract translation: 提供了一个低压差调节器。 低压差调节器包括一个包括串联连接的奇数运算放大器的放大器，以及一个输出单元，包括一个由放大器的输出端工作的通过晶体管，并产生一个要加到负载上的输出电压， 其中所述传输晶体管是N沟道晶体管，并且所述放大器控制所述奇数个运算放大器之一的输出端与所述输出单元之间的反馈环路增益。 反馈环路增益可以独立于传输晶体管的跨导电阻来控制，由此即使在改变负载和输入电压的情况下也可以产生稳定的输出电压，并且可以简化设计参数。

    METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS IN BULK SEMICONDUCTOR SUBSTRATES
    28.
    发明申请
    METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS IN BULK SEMICONDUCTOR SUBSTRATES 有权
    在半导体衬底中制造FINFET集成电路的方法

    公开(公告)号：US20130045580A1

    公开(公告)日：2013-02-21

    申请号：US13210086

    申请日：2011-08-15

    Applicant: Jin Cho

    Inventor： Jin Cho

    IPC: H01L21/336 ,  H01L21/762 ,  B82Y40/00

    CPC classification number: H01L21/823431 ,  H01L21/76224 ,  H01L29/66545

    Abstract: Methods are provided for fabricating FinFETs that avoid thickness uniformity problems across a die or a substrate. One method includes providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines. The substrate is etched to form a plurality of fins, each of the fins extending uniformly across the width of the chips. An oxide is deposited to fill between the fins and is etched to recess the top of the oxide below the top of the fins. An isolation hard mask is deposited and patterned overlying the plurality of fins and is used as an etch mask to etch trenches in the substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins. The trenches are filled with an insulating material to isolate between adjacent active areas.

    Abstract translation: 提供了用于制造FinFET的方法，其避免了晶片或衬底上的厚度均匀性问题。 一种方法包括提供划分成多个芯片的半导体衬底，每个芯片由划线限定。 蚀刻基板以形成多个翅片，每个翅片均匀地延伸穿过芯片的宽度。 沉积氧化物以填充在翅片之间并且被蚀刻以使在该翅片顶部下方的氧化物的顶部凹陷。 隔离硬掩模被沉积并且图案覆盖在多个翅片上并被用作蚀刻掩模以蚀刻限定多个有效区域的衬底中的沟槽，多个有效区域中的每一个包括至少一部分至少一个 翅片 沟槽填充绝缘材料以隔离相邻的活性区域。

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