公开(公告)号：US20090079060A1

公开(公告)日：2009-03-26

申请号：US11860226

申请日：2007-09-24

Applicant: GERALD K. BARTLEY ,  Darryl L. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： GERALD K. BARTLEY ,  Darryl L. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: H01L23/15 ,  H01L21/98

CPC classification number: H01L21/563 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81365 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2924/0001 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2224/13099

Abstract: A method of making an integrated circuit package includes forming a through hole in an integrated circuit and assembling a die containing the integrated circuit on a carrier so that the die is mechanically and electrically connected to the carrier. Thereafter, an underfill material is dispensed between the die and the carrier via the through hole.

Abstract translation: 制造集成电路封装的方法包括在集成电路中形成通孔并将包含集成电路的管芯组装在载体上，使得管芯机械地和电连接到载体上。 此后，通过通孔将底部填充材料分配在模具和载体之间。

公开(公告)号：US20090058425A1

公开(公告)日：2009-03-05

申请号：US11848652

申请日：2007-08-31

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G01R31/02

CPC classification number: G01R31/2808 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/111 ,  H05K2201/09063

Abstract: An apparatus for testing electrical continuity of a surface mounted (SMT) electrical board includes: a printed wiring board having a first surface and an opposite second surface; a conductive signal line disposed on each of the first and second surfaces of the printed wiring board; an electrical component disposed on and electrically connected to the conductive signal line on the first surface; and a through hole extending through the printed wiring board and the conductive signal line on the second surface of the printed wiring board exposing a surface side of the conductive signal line facing the first surface of the printed wiring board. The through hole is unplated in an inside bore defining the through hole and the through hole allows direct access to the conductive signal line on the first surface to test continuity of the conductive signal line on the first surface connected to the electrical component from the second surface of the printed wiring board.

Abstract translation: 一种用于测试表面安装（SMT）电气板的电气连续性的装置包括：具有第一表面和相对的第二表面的印刷线路板; 布置在所述印刷电路板的所述第一表面和所述第二表面中的每一个上的导电信号线; 设置在第一表面上并电连接到第一表面上的导电信号线的电气部件; 以及延伸穿过印刷线路板的通孔和印刷线路板的第二表面上的导电信号线，其暴露导电信号线的面对印刷线路板的第一表面的表面侧。 在限定通孔的内孔中没有通孔，并且通孔允许直接进入第一表面上的导电信号线，以测试从第二表面连接到电气部件的第一表面上的导电信号线的连续性 的印刷线路板。

公开(公告)号：US07477568B2

公开(公告)日：2009-01-13

申请号：US12034773

申请日：2008-02-21

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G11C8/00

CPC classification number: G11C5/063 ,  G11C7/1048 ,  G11C7/1066

Abstract: A double-data-rate two synchronous dynamic random access (DDR2 ) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output path and a low-speed output path are coupled together by an output coupling and further coupled to the common output of the memory core.

Abstract translation: 双数据速率两同步动态随机存取（DDR2）存储器电路包括低速输入路径和通过输入耦合耦合到其上的高速输入路径并形成公共输入，公共输入耦合到存储器核心 存储器芯具有公共输出，其中高速输出路径和低速输出路径通过输出耦合耦合在一起并进一步耦合到存储器核心的公共输出端。

公开(公告)号：US07810065B2

公开(公告)日：2010-10-05

申请号：US11844861

申请日：2007-08-24

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  Trevor J. Timpane

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  Trevor J. Timpane

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/40

Abstract: System and method for designing an electronic package. A placement manager receives a physical design of an electronic package from a packaging design tool. The placement manager receives design constraints regarding the physical design for the electronic package. The placement manager inserts specifications for at least one de-gassing opening in the physical design for the electronic package, wherein the specification for at least one de-gassing opening are created in accordance with said design constraints regarding said physical design of said electronic package. The placement manager outputs an updated physical design of the electronic package.

Abstract translation: 用于设计电子封装的系统和方法。 布置管理员从包装设计工具接收电子包装的物理设计。 放置管理器接收关于电子封装的物理设计的设计约束。 布置管理器在电子封装的物理设计中插入用于至少一个除气开口的规格，其中根据关于所述电子封装的所述物理设计的所述设计约束创建至少一个除气开口的规格。 布局管理器输出电子包的更新的物理设计。

公开(公告)号：US20100026337A1

公开(公告)日：2010-02-04

申请号：US12181376

申请日：2008-07-29

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

IPC: H03K19/00

CPC classification number: G06F21/75 ,  G06F21/86 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: An integrated circuit assembly comprising a microchip that shares an interdependent function with a second, stacked microchip. Alternation of the physical arrangement or functionality of the microchips may initiate a defense action intended to protect security sensitive circuitry associated with one of the microchips. The microchips may communicate using through-silicon vias or other interconnects.

Abstract translation: 一种集成电路组件，包括与第二堆叠微芯片共享相互依赖功能的微芯片。 微芯片的物理布置或功能的交替可以启动旨在保护与微芯片中的一个相关联的安全敏感电路的防御动作。 微芯片可以使用硅通孔或其他互连进行通信。

公开(公告)号：US20100026336A1

公开(公告)日：2010-02-04

申请号：US12181367

申请日：2008-07-29

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

IPC: H03K19/00

CPC classification number: G06F21/86 ,  G06F21/75 ,  H01L23/57 ,  H01L2224/32225

Abstract: An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected.

Abstract translation: 检测微芯片篡改的集成电路组件和相关联的方法可以包括与导电层电连通的多个连接。 防御性电路可能会阻止微芯片的分析，其中连接不再连接到导电层。 防御性电路可以类似地启动，其中连接不想与导电层电连通的连接是连接的。

公开(公告)号：US20100025479A1

公开(公告)日：2010-02-04

申请号：US12181401

申请日：2008-07-29

Applicant: Gerald K Bartley ,  Darryl J. Becker ,  Todd A. Christensen ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

Inventor： Gerald K Bartley ,  Darryl J. Becker ,  Todd A. Christensen ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

IPC: G06K19/06

CPC classification number: G06F21/87

Abstract: A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation.

Abstract translation: 一种方法和装置包括掺杂在微芯片内的导电材料，其在离子存在下累积可检测的电荷。 这样的离子可能由聚焦离子束或其他不受欢迎的技术开发而产生。 感测嵌入的掺杂材料中的电荷积累的电路可以启动旨在击败篡改操作的防御动作。

公开(公告)号：US20090305463A1

公开(公告)日：2009-12-10

申请号：US12134728

申请日：2008-06-06

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: H01L21/58

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552

Abstract: A method for thermal optimization comprising the steps of stacking a first chip layer and a second chip layer wherein the second chip layer is rotated in relation to the first chip layer wherein a first hot spot on the first chip layer and a second hot spot on the second chip layer are not spatially aligned; routing a signal input through the first chip layer from a first chip pad on the first chip layer to a first silicon via so as to form a physical input to output twist and a first signal output; and routing the first signal output from the first chip layer through a second chip layer from a second chip pad on the second chip layer to a second silicon via so as to form a second signal output.

Abstract translation: 一种用于热优化的方法，包括以下步骤：堆叠第一芯片层和第二芯片层，其中第二芯片层相对于第一芯片层旋转，其中第一芯片层上的第一热点和第一芯片层上的第二热点 第二芯片层不在空间上对准; 将通过第一芯片层输入的信号从第一芯片层上的第一芯片焊盘传送到第一硅通孔，以便形成物理输入以输出扭曲和第一信号输出; 以及将从第一芯片层输出的第一信号通过第二芯片层从第二芯片层上的第二芯片焊盘路由到第二硅通孔，以形成第二信号输出。

公开(公告)号：US20090031067A1

公开(公告)日：2009-01-29

申请号：US11829250

申请日：2007-07-27

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  John M. Borkenhagen ,  Paul E. Dahlen ,  Philip R. Germann ,  William P. Hovis ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  John M. Borkenhagen ,  Paul E. Dahlen ,  Philip R. Germann ,  William P. Hovis ,  Mark O. Maxson

IPC: G06F13/36 ,  G06F12/00

CPC classification number: G06F13/1684

Abstract: A data communications apparatus includes a central device and a plurality of communication devices. The central device includes a plurality of central port pairs, in which each central port pair includes an input port and an output port. The plurality of communication devices is arranged in a spoke and ring configuration, in which each communication device is part of a communication spoke. Each communication spoke is in communication with a different central port pair. Each communication device is also a part of a communication ring, so that each communication device in a selected communication ring belongs to a different communication spoke.

Abstract translation: 数据通信装置包括中央装置和多个通信装置。 中央设备包括多个中心端口对，其中每个中心端口对包括输入端口和输出端口。 多个通信设备被布置成辐条和环配置，其中每个通信设备是通信辐条的一部分。 每个通话都与不同的中心端口对通信。 每个通信设备也是通信环的一部分，使得所选通信环中的每个通信设备属于不同的通信语音。

公开(公告)号：US20080276214A1

公开(公告)日：2008-11-06

申请号：US11742970

申请日：2007-05-01

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G06F17/50

CPC classification number: H01L23/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Connection assignments of differential signals within an integrated circuit (IC) package are automatically made in the design and manufacturing process of the IC package, for use in automated computing systems. Either predefined pairs of pins at both ends or pairs of pins automatically paired or a combination of both are used in the creation of an imaginary pin or midpoint between the pair. Then the point-to-point connections of the pair are automatically detangled. Once the imaginary midpoint-to-midpoint connections are created, the real differential connections can then be assigned.

Abstract translation: 集成电路（IC）封装中的差分信号的连接分配在IC封装的设计和制造过程中自动进行，用于自动化计算系统。 两端的一对预定义的引脚对或两对引脚自动配对或两者的组合用于在该对之间创建假想引脚或中点。 然后，该对的点对点连接将自动错位。 一旦创建了虚拟的中点到中点连接，则可以分配实际的差分连接。