公开(公告)号：US20070134926A1

公开(公告)日：2007-06-14

申请号：US11635223

申请日：2006-12-07

Applicant: O. Kyun Kwon ,  Mi Ran Park ,  Won Seok Han ,  Hyun Woo Song

Inventor： O. Kyun Kwon ,  Mi Ran Park ,  Won Seok Han ,  Hyun Woo Song

IPC: H01L21/302

CPC classification number: H01L21/30621 ,  H01S5/183 ,  H01S5/2081

Abstract: Provided are an etching method for a multi-layered structure of semiconductors in groups III-V and a method of manufacturing a VCSEL using the etching method. According to the etching method, a stacked structure including a first semiconductor layer and a second semiconductor layer is exposed to a plasma of a mixture consisting of Cl2, Ar, CH4, and H2 to etch the stacked structure, so that a mirror layer of the VCSEL is formed. The first semiconductor layer is formed of a semiconductor in groups III-V and the second semiconductor layer is formed of a semiconductor in groups III-V, other than the semiconductor of the first semiconductor layer. At least part of a lower mirror layer, a lower electrode layer, an optical gain layer, an upper electrode layer, and an upper mirror layer is etched using one time of an etching process, so that a clean and smooth etched surface is obtained.

Abstract translation: 提供了III-V族半导体的多层结构的蚀刻方法和使用该蚀刻方法制造VCSEL的方法。 根据蚀刻方法，将包括第一半导体层和第二半导体层的堆叠结构暴露于由Cl 2，Ar，CH 4， 和H 2 N以蚀刻堆叠结构，从而形成VCSEL的镜层。 第一半导体层由III-V族的半导体形成，第二半导体层由除了第一半导体层的半导体之外的III-V族的半导体形成。 使用一次蚀刻工艺蚀刻下镜面层，下电极层，光增益层，上电极层和上镜层的至少一部分，从而获得清洁且光滑的蚀刻表面。

公开(公告)号：US07183151B2

公开(公告)日：2007-02-27

申请号：US10919416

申请日：2004-08-17

Applicant: Mi Ran Park

Inventor： Mi Ran Park

IPC: H01L21/336

CPC classification number: H01L29/66462 ,  H01L21/0331 ,  H01L21/28 ,  H01L21/32051 ,  H01L29/2003

Abstract: Provided is a method for fabricating a filed effect transistor, the method comprising: depositing a first semiconductor layer and a second semiconductor layer on a substrate in sequence, which have a different bandgap from each other, and patterning the second semiconductor layer to have a mesa structure; forming a first resist pattern to expose the second semiconductor layer of a region where source and drain are to be formed; depositing a metal on a whole upper surface, and forming metallic source and drain by performing a lift-off process; performing heat treatment to form an ohmic contact between the source and the second semiconductor layer, and between the drain and the semiconductor layer; forming an insulating layer on the whole upper surface including the source and the drain, and forming a second photoresist pattern to expose the insulating layer at a portion where a gate is to be formed; exposing the second semiconductor layer at the portion where the gate is to be formed by etching the exposed portion of the insulating layer; and depositing the metal on the whole upper surface in a state that the temperature of the substrate is lowered to perform low temperature vacuum deposition, and forming a metallic gate by performing a lift-off process and an insulating layer removing process.

Abstract translation: 提供了一种制造场效应晶体管的方法，所述方法包括：依次在基板上沉积第一半导体层和第二半导体层，所述第一半导体层和第二半导体层彼此具有不同的带隙，并且将第二半导体层图案化以具有台面 结构体; 形成第一抗蚀剂图案以暴露要形成源极和漏极的区域的第二半导体层; 在整个上表面上沉积金属，并通过执行剥离工艺形成金属源和漏极; 进行热处理以在源极和第二半导体层之间以及在漏极和半导体层之间形成欧姆接触; 在包括所述源极和漏极的整个上表面上形成绝缘层，并且形成第二光致抗蚀剂图案以在要形成栅极的部分处暴露所述绝缘层; 通过蚀刻绝缘层的暴露部分，在要形成栅极的部分暴露第二半导体层; 并且在基板的温度降低以进行低温真空沉积的状态下将金属沉积在整个上表面上，并且通过执行剥离处理和绝缘层去除工艺来形成金属栅极。

公开(公告)号：US20130163916A1

公开(公告)日：2013-06-27

申请号：US13487807

申请日：2012-06-04

Applicant: Hyun Soo KIM ,  Jong Sool Jeong ,  Mi-Ran Park ,  Byungseok Choi ,  O-Kyun Kwon

Inventor： Hyun Soo KIM ,  Jong Sool Jeong ,  Mi-Ran Park ,  Byungseok Choi ,  O-Kyun Kwon

IPC: G02B6/12 ,  H01L21/02

CPC classification number: G02B6/43 ,  G02B6/12004 ,  G02B6/1228 ,  G02B6/4224 ,  G02B6/4232

Abstract: Disclosed are an optical waveguide platform with integrated active transmission device and monitoring photodiode. The optical waveguide platform with hybrid integrated optical transmission device and optical active device includes an optical waveguide region formed by stacking a lower cladding layer, a core layer and an upper cladding layer on a substrate; a trench region formed by etching a portion of the optical waveguide region; and a spot expanding region formed on the core layer in the optical waveguide region, in which the optical transmission device is mounted in the trench region and the optical active device is flip-chip bonded to the spot expanding region. The monitoring photodiode is flip-chip bonded to the spot expanding region of the core layer of the optical waveguide, thereby monitoring output light including an optical coupling loss that occurs during flip-chip bonding.

Abstract translation: 公开了一种具有集成主动传输装置和监测光电二极管的光波导平台。 具有混合集成光传输装置和光学有源装置的光波导平台包括通过在基板上层叠下包层，芯层和上包层而形成的光波导区域; 通过蚀刻光波导区域的一部分形成的沟槽区域; 以及形成在光波导区域的芯层上的点扩展区域，其中光传输装置安装在沟槽区域中，并且光学有源器件被倒装芯片接合到点扩展区域。 监视光电二极管被倒装芯片接合到光波导的芯层的点扩展区域，从而监视包括在倒装芯片接合期间发生的光耦合损耗的输出光。

公开(公告)号：US20110150016A1

公开(公告)日：2011-06-23

申请号：US12973481

申请日：2010-12-20

Applicant: Mi-Ran PARK ,  O-Kyun KWON ,  byung-seok CHOI ,  Dae Kon OH

Inventor： Mi-Ran PARK ,  O-Kyun KWON ,  byung-seok CHOI ,  Dae Kon OH

IPC: H01S3/10

CPC classification number: H01S5/423 ,  H01S5/0085 ,  H01S5/02415 ,  H01S5/18341 ,  H01S5/18358 ,  H01S5/4012 ,  H01S5/4087 ,  H01S5/50

Abstract: Provided is a tunable laser module emitting an optical signal having high speed, high power and wideband wavelength tuning. The tunable laser module includes a laser array configured to emit an optical signal having a plurality of different lasing wavelengths, a temperature controller configured to change a temperature of the laser array, and an optical integration device configured to modulate or amplify the optical signal at a side of the laser array opposing the temperature controller.

Abstract translation: 提供了一种发射具有高速度，高功率和宽带波长调谐的光信号的可调谐激光模块。 可调谐激光器模块包括配置成发射具有多个不同的激光波长的光信号的激光器阵列，配置成改变激光器阵列的温度的温度控制器，以及配置成在一个或多个激光器阵列处调制或放大光信号的光学积分装置 激光器阵列的一侧与温度控制器相对。

公开(公告)号：US20100278477A1

公开(公告)日：2010-11-04

申请号：US12746167

申请日：2008-06-03

Applicant: Jeong-Woo Park ,  Gyung-Ock Kim ,  Mi-Ran Park ,  Jong-Bum You

Inventor： Jeong-Woo Park ,  Gyung-Ock Kim ,  Mi-Ran Park ,  Jong-Bum You

IPC: G02B6/12 ,  G02B6/34

CPC classification number: G02F1/218 ,  G02F2001/212 ,  G02F2201/302

Abstract: Provided is a semiconductor integrated circuit. The semiconductor integrated circuit includes a semiconductor pattern disposed on a substrate and including an optical waveguide part and a pair of recessed portions. The optical waveguide part has a thickness ranging from about 0.05 m to about 0.5 μm. The recessed portions are disposed on both sides of the optical waveguide part and have a thinner thickness than the optical waveguide part. A first doped region and a second doped region are disposed in the recessed portions, respectively. The first and second doped regions are doped with a first conductive type dopant and a second conductive type dopant, respectively. An intrinsic region is formed in at least the optical waveguide part to contact the first and second doped regions.

Abstract translation: 提供了一种半导体集成电路。 半导体集成电路包括设置在基板上并且包括光波导部分和一对凹部的半导体图案。 光波导部分的厚度范围为约0.05μm至约0.5μm。 凹部设置在光波导部分的两侧，并且具有比光波导部分更薄的厚度。 第一掺杂区域和第二掺杂区域分别设置在凹部中。 第一和第二掺杂区域分别掺杂有第一导电型掺杂剂和第二导电型掺杂剂。 在至少光波导部分中形成本征区域以接触第一和第二掺杂区域。

公开(公告)号：US07776752B2

公开(公告)日：2010-08-17

申请号：US11635223

申请日：2006-12-07

Applicant: O Kyun Kwon ,  Mi Ran Park ,  Won Seok Han ,  Hyun Woo Song

Inventor： O Kyun Kwon ,  Mi Ran Park ,  Won Seok Han ,  Hyun Woo Song

IPC: H01L21/302

CPC classification number: H01L21/30621 ,  H01S5/183 ,  H01S5/2081

Abstract: Provided are an etching method for a multi-layered structure of semiconductors in groups III-V and a method of manufacturing a VCSEL using the etching method. According to the etching method, a stacked structure including a first semiconductor layer and a second semiconductor layer is exposed to a plasma of a mixture consisting of Cl2, Ar, CH4, and H2 to etch the stacked structure, so that a mirror layer of the VCSEL is formed. The first semiconductor layer is formed of a semiconductor in groups III-V and the second semiconductor layer is formed of a semiconductor in groups III-V, other than the semiconductor of the first semiconductor layer. At least part of a lower mirror layer, a lower electrode layer, an optical gain layer, an upper electrode layer, and an upper mirror layer is etched using one time of an etching process, so that a clean and smooth etched surface is obtained.

Abstract translation: 提供了III-V族半导体的多层结构的蚀刻方法和使用该蚀刻方法制造VCSEL的方法。 根据蚀刻方法，将包括第一半导体层和第二半导体层的堆叠结构暴露于由Cl 2，Ar，CH 4和H 2组成的混合物的等离子体中，以蚀刻层叠结构，使得 形成VCSEL。 第一半导体层由III-V族的半导体形成，第二半导体层由除了第一半导体层的半导体之外的III-V族的半导体形成。 使用一次蚀刻工艺蚀刻下镜面层，下电极层，光增益层，上电极层和上镜层的至少一部分，从而获得清洁且光滑的蚀刻表面。

公开(公告)号：US20090154868A1

公开(公告)日：2009-06-18

申请号：US12117707

申请日：2008-05-08

Applicant: Mi-Ran PARK ,  O-Kyun Kwon ,  Jeong-Woo Park ,  Gyung-Ock Kim

Inventor： Mi-Ran PARK ,  O-Kyun Kwon ,  Jeong-Woo Park ,  Gyung-Ock Kim

IPC: G02F1/295

CPC classification number: G02F1/01708 ,  B82Y20/00 ,  G02F1/025 ,  G02F2001/0152 ,  G02F2201/302 ,  G02F2201/34 ,  G02F2203/02

Abstract: Provided are semiconductor opto-electronic integrated circuits and methods of forming the same. The semiconductor opto-electronic integrated circuit includes: an optical waveguide disposed on a substrate and including an input terminal and an output terminal; an optical grating formed on the optical waveguide; and an optical active device disposed on the optical grating and receiving an optical signal from the optical waveguide through the optical grating to modulate the optical signal.

Abstract translation: 提供半导体光电集成电路及其形成方法。 半导体光电集成电路包括：设置在基板上并包括输入端子和输出端子的光波导; 形成在光波导上的光栅; 以及设置在光栅上的光学有源器件，并通过光栅从光波导接收光信号，以调制光信号。

公开(公告)号：US09229183B2

公开(公告)日：2016-01-05

申请号：US14012384

申请日：2013-08-28

Applicant: Mi-Ran Park ,  Jong Sool Jeong ,  Hyun Soo Kim ,  Byungseok Choi ,  Young Tak Han ,  O-Kyun Kwon

Inventor： Mi-Ran Park ,  Jong Sool Jeong ,  Hyun Soo Kim ,  Byungseok Choi ,  Young Tak Han ,  O-Kyun Kwon

IPC: H04B10/60 ,  G02B6/42

CPC classification number: G02B6/4274 ,  G02B6/4249 ,  G02B6/4263 ,  G02B6/4279

Abstract: Disclosed is a multi-channel receiver optical sub assembly. The a multi-channel receiver optical sub assembly includes: a multi-channel PD array, in which a plurality of photodiodes (PDs) disposed on a first capacitor, and including receiving areas disposed at centers thereof and anode electrode pads arranged in an opposite direction at an angle of 180 degrees based on the receiving areas between the adjacent PDs is monolithically integrated; a plurality of transimpedance amplifiers (TIAs) arranged on a plurality of second capacitors, respectively, and connected with the anode pads of the respective PDs through wire bonding; a submount on which the first capacitor.

Abstract translation: 公开了一种多通道接收机光学子组件。 多通道接收机光学子组件包括：多通道PD阵列，其中设置在第一电容器上的多个光电二极管（PD），并且包括设置在其中心处的接收区域和布置在相反方向的阳极电极焊盘 基于相邻PD之间的接收区域以180度的角度被整体地集成; 分别布置在多个第二电容器上并通过引线接合与相应PD的阳极焊盘连接的多个跨阻抗放大器（TIA）; 第一电容器的基座。

公开(公告)号：US20150063832A1

公开(公告)日：2015-03-05

申请号：US14012384

申请日：2013-08-28

Applicant: Mi-Ran PARK ,  Jong Sool JEONG ,  Hyun Soo KIM ,  Byungseok CHOI ,  Young Tak HAN ,  O-Kyun KWON

Inventor： Mi-Ran PARK ,  Jong Sool JEONG ,  Hyun Soo KIM ,  Byungseok CHOI ,  Young Tak HAN ,  O-Kyun KWON

IPC: H04B10/60 ,  H04J14/02

CPC classification number: G02B6/4274 ,  G02B6/4249 ,  G02B6/4263 ,  G02B6/4279

Abstract: Disclosed is a multi-channel receiver optical sub assembly. The a multi-channel receiver optical sub assembly includes: a multi-channel PD array, in which a plurality of photodiodes (PDs) disposed on a first capacitor, and including receiving areas disposed at centers thereof and anode electrode pads arranged in an opposite direction at an angle of 180 degrees based on the receiving areas between the adjacent PDs is monolithically integrated; a plurality of transimpedance amplifiers (TIAs) arranged on a plurality of second capacitors, respectively, and connected with the anode pads of the respective PDs through wire bonding; a submount on which the first capacitor.

Abstract translation: 公开了一种多通道接收机光学子组件。 多通道接收机光学子组件包括：多通道PD阵列，其中设置在第一电容器上的多个光电二极管（PD），并且包括设置在其中心处的接收区域和布置在相反方向的阳极电极焊盘 基于相邻PD之间的接收区域以180度的角度被整体地集成; 分别布置在多个第二电容器上并通过引线接合与相应PD的阳极焊盘连接的多个跨阻抗放大器（TIA）; 第一电容器的基座。

公开(公告)号：US20130004455A1

公开(公告)日：2013-01-03

申请号：US13173783

申请日：2011-06-30

Applicant: Soo-Chang SONG ,  Thrimoorthy Potta ,  Mi-Ran Park

Inventor： Soo-Chang SONG ,  Thrimoorthy Potta ,  Mi-Ran Park

IPC: A61K31/80 ,  C12N9/96 ,  C08G69/48 ,  A61P19/04 ,  A61P9/00

CPC classification number: A61L27/18 ,  A61L27/52 ,  A61L27/54 ,  A61L2300/80 ,  C08G79/02 ,  C08G79/025 ,  C08J3/075 ,  C08J2385/02 ,  C08L85/02

Abstract: Provided are a use of chemically-crosslinkable, poly(organophosphazene)s for biomaterials, chemically-crosslinkable poly(organophosphazene)s with a physiologically active substance covalently-bonded thereto, a use thereof for biomaterials, and a process for preparing the same. The chemical crosslinkings can be made by UV irradiation, and/or a crosslinker, and/or an additive, and/or an enzyme, and/or a mixing of at least one polymer.

Abstract translation: 提供了用于生物材料的化学交联的聚（有机膦腈），与共价键合的生理活性物质的化学交联的聚（有机膦腈），其生物材料的用途及其制备方法的用途。 化学交联可以通过UV照射和/或交联剂，/或添加剂和/或酶进行，和/或至少一种聚合物的混合。