公开(公告)号：US09799606B2

公开(公告)日：2017-10-24

申请号：US14637640

申请日：2015-03-04

Applicant: Sang Hoon Ahn ,  Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Nae-In Lee

Inventor： Sang Hoon Ahn ,  Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Nae-In Lee

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first conductive pattern on a substrate, an insulating diffusion barrier layer conformally covering a surface of the first conductive pattern, the insulation diffusion barrier layer exposed by an air gap region adjacent to a sidewall of the first conductive pattern, and a second conductive pattern on the first conductive pattern, the second conductive pattern penetrating the insulating diffusion barrier layer so as to be in contact with the first conductive pattern.

公开(公告)号：US20160329242A1

公开(公告)日：2016-11-10

申请号：US15048993

申请日：2016-02-19

Applicant: Thomas OSZINDA ,  Tae-Jin YIM ,  Sang-Hoon AHN ,  Nae-In LEE

Inventor： Thomas OSZINDA ,  Tae-Jin YIM ,  Sang-Hoon AHN ,  Nae-In LEE

IPC: H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1047

Abstract: In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.

Abstract translation: 在形成布线结构的方法中，在基板上形成绝缘中间层。 绝缘中间层包括开口，并且其中分布有孔并在其表面露出。 将绝缘中间层暴露于硅烷化合物以在绝缘中间层的表面和开口的侧壁上形成孔密封层。 填充开口的导电图案形成在孔密封层上。

公开(公告)号：US09397216B2

公开(公告)日：2016-07-19

申请号：US14938172

申请日：2015-11-11

Applicant: Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

Inventor： Dong-Suk Shin ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US20160141246A1

公开(公告)日：2016-05-19

申请号：US14924217

申请日：2015-10-27

Applicant: Jin-Nam Kim ,  Tsukasa Matsuda ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Nae-In Lee ,  Jong-Jin Lee

Inventor： Jin-Nam Kim ,  Tsukasa Matsuda ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Nae-In Lee ,  Jong-Jin Lee

IPC: H01L23/522

CPC classification number: H01L23/485 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76882 ,  H01L23/49822 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：第一层间绝缘层，包括第一沟槽，在衬底上，沿着侧壁形成的第一衬里层和第一沟槽的底表面，并且包括贵金属，贵金属属于第五周期之一， 是国际纯粹和应用化学联合会（IUPAC）编号之后的第六周期，属于周期图的第八至第十组之一，以及填充第一衬里层上的第一沟槽的第一金属线， 所述第一金属线的顶表面朝向所述第一沟槽的底表面具有凸形形状。

公开(公告)号：US20160064565A1

公开(公告)日：2016-03-03

申请号：US14938172

申请日：2015-11-11

Applicant: Dong-Suk SHIN ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM ,  Nae-In LEE

Inventor： Dong-Suk SHIN ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM ,  Nae-In LEE

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

公开(公告)号：US20150064870A1

公开(公告)日：2015-03-05

申请号：US14534475

申请日：2014-11-06

Applicant: Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

Inventor： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/161 ,  H01L29/165 ,  H01L21/306 ,  H01L29/16

CPC classification number: H01L27/1104 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

Abstract translation: 在半导体器件中，第一有源区具有第一和第四形状，第二有源区具有第二“S”形。 当垂直于衬底并将第一栅电极的侧表面通过第一区域的线被定义为第一垂直线时，当垂直于衬底并通过第二栅电极的侧表面的线 在第二区域被定义为第二垂直线时，当第一垂直线和第一沟槽之间的最短距离被定义为第一水平距离时，并且当第二垂直线和第二沟槽之间的最短距离被定义为 第二水平距离，第一水平距离和第二水平距离之间的差等于或小于1nm。

公开(公告)号：US08841184B2

公开(公告)日：2014-09-23

申请号：US13661748

申请日：2012-10-26

Applicant: Jong-Ho Lee ,  Nae-In Lee

Inventor： Jong-Ho Lee ,  Nae-In Lee

IPC: H01L21/8238 ,  H01L29/788 ,  H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US20140138745A1

公开(公告)日：2014-05-22

申请号：US14033718

申请日：2013-09-23

Applicant: Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

Inventor： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成沟槽，并且沟槽可以包括有源区的切口部分。 所述方法还可以包括在沟槽中形成嵌入的应力源。 嵌入式应力器可以包括下半导体层和上半导体层，其宽度比下半导体层的宽度窄。 上半导体层的一侧可以不与下半导体层的一侧对准，并且上半导体层的最上表面可以高于有源区的最上表面。

公开(公告)号：US07863142B2

公开(公告)日：2011-01-04

申请号：US12078750

申请日：2008-04-04

Applicant: Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

Inventor： Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.

公开(公告)号：US20100065919A1

公开(公告)日：2010-03-18

申请号：US12621079

申请日：2009-11-18

Applicant: Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

Inventor： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC: H01L27/092

CPC classification number: H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

Abstract translation: 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。