公开(公告)号：US5540777A

公开(公告)日：1996-07-30

申请号：US541284

申请日：1995-10-12

Applicant: Steven G. Barbee ,  Jonathan D. Chapple-Sokol ,  Richard A. Conti ,  Richard Hsiao ,  James A. O'Neill ,  Narayana V. Sarma ,  Donald L. Wilson ,  Justin W.-C. Wong ,  Steven P. Zuhoski

Inventor： Steven G. Barbee ,  Jonathan D. Chapple-Sokol ,  Richard A. Conti ,  Richard Hsiao ,  James A. O'Neill ,  Narayana V. Sarma ,  Donald L. Wilson ,  Justin W.-C. Wong ,  Steven P. Zuhoski

IPC: C23C16/40 ,  C23C16/448 ,  C23C16/52 ,  H01L21/205 ,  H01L21/31 ,  H01L21/316 ,  C23C16/00

CPC classification number: C23C16/403 ,  C23C16/4481 ,  C23C16/52

Abstract: A process and apparatus for Al.sub.2 O.sub.3 CVD on silicon wafers using aluminum tri-isopropoxide in a high-volume production environment is presented. The conditions required to use ATI in a production environment and provide maximum utilization of ATI are first of all delivery of ATI via direct evaporation. The ATI source bottle is pumped out (bypassing substrates) until propene and isopropanol signals are reduced to 1% of process pressure before start of aluminum oxide deposition. Either IR spectroscopy or mass spectrometry can be used to provide a control signal to the microprocessor controller. Heating the supplied tetramer to 120.degree. C. for two hours assures complete conversion to trimer. The ATI is stored at 90.degree. C. to minimize decomposition during idle periods and allow recovery of trimer upon return to 120.degree. C. for two hours. During periods of demand, the ATI is held at 120.degree. C. to minimize decomposition.

Abstract translation: 介绍了在大批量生产环境中使用三异丙氧基铝的硅晶片上Al2O3 CVD的工艺和装置。 在生产环境中使用ATI并提供ATI的最大利用率所需的条件首先通过直接蒸发传送ATI。 在开始氧化铝沉积之前，将ATI源瓶泵出（旁路基板），直到丙烯和异丙醇信号降低到过程压力的1％。 可以使用红外光谱或质谱法向微处理器控制器提供控制信号。 将供应的四聚体加热至120℃保持两小时，确保完全转化为三聚体。 将ATI储存在90℃以使空闲期间的分解最小化，并允许在回到120℃回收三聚体两小时。 在需求期间，ATI保持在120℃以最小化分解。

公开(公告)号：US5268069A

公开(公告)日：1993-12-07

申请号：US895493

申请日：1992-06-08

Applicant: Jonathan D. Chapple-Sokol ,  Richard A. Conti ,  David E. Kotecki ,  Andrew H. Simon ,  Manu Tejwani

Inventor： Jonathan D. Chapple-Sokol ,  Richard A. Conti ,  David E. Kotecki ,  Andrew H. Simon ,  Manu Tejwani

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/00

CPC classification number: H01L21/02046 ,  H01L21/02049 ,  H01L21/31116

Abstract: Anhydrous ammonium fluoride is used as a safe source of hydrogen fluoride for etching native or other silicon dioxide layers from silicon substrates. Heating the anhydrous ammonium fluoride above its sublimation temperature results in the generation of hydrogen fluoride gas which etches the silicon dioxide. Controlled amounts of water vapor are used during the etch reaction to ensure complete etching of the thin oxide layers down to within hundredths of a monolayer and to achieve precise etch rate control.

Abstract translation: 无水氟化铵用作氟化氢的安全源，用于从硅衬底蚀刻天然或其他二氧化硅层。 在其升华温度以上加热无水氟化铵导致产生二氧化硅蚀刻的氟化氢气体。 在蚀刻反应期间使用受控量的水蒸气，以确保将薄氧化物层完全蚀刻到百分之几以下的单层并且实现精确的蚀刻速率控制。

公开(公告)号：US5134963A

公开(公告)日：1992-08-04

申请号：US784160

申请日：1991-10-28

Applicant: Steven G. Barbee ,  Jonathan D. Chapple-Sokol ,  Richard A. Conti ,  David E. Kotecki

Inventor： Steven G. Barbee ,  Jonathan D. Chapple-Sokol ,  Richard A. Conti ,  David E. Kotecki

IPC: C23C16/52 ,  C23C16/44 ,  C23C16/455 ,  C30B25/14 ,  H01L21/205

CPC classification number: C23C16/45565 ,  C23C16/455 ,  C23C16/45504 ,  C30B25/14

Abstract: An injector with a convex wall surface facing the susceptor directs vapor toward a wafer held by a susceptor producing a generally laminar flow across the surface of the wafer that in combination with the convex wall surface prevents formation of recirculation cells in the region between the wafer and the injector.

公开(公告)号：US20090311855A1

公开(公告)日：2009-12-17

申请号：US12544425

申请日：2009-08-20

Applicant: Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

Inventor： Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

IPC: H01L21/28

CPC classification number: H01L21/823807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823864 ,  H01L29/7843

Abstract: A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.

Abstract translation: 提供了在金属氧化物半导体场效应晶体管（MOSFET）中制造栅极结构的方法及其结构。 MOSFET可以是n掺杂或p掺杂的。 设置在基板上的栅极结构包括多个栅极。 多个栅极中的每一个与相邻栅极分开一垂直空间。 该方法将填充每个垂直空间的至少一个双层衬垫沉积在栅极结构上。 双层衬垫包括至少两个薄的高密度等离子体（HDP）膜。 两种HDP膜的沉积在单个HDP化学气相沉积（CVD）工艺中发生。 双层衬垫具有有利于与等离子体增强化学气相沉积（PECVD）膜耦合以在栅极结构中形成三层或二次层膜堆叠的性质。

公开(公告)号：US20090101980A1

公开(公告)日：2009-04-23

申请号：US11875222

申请日：2007-10-19

Applicant: Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

Inventor： Richard A. Bruff ,  Richard A. Conti ,  Denise Pendleton-Lipinski ,  Amanda L. Tessier ,  Brian L. Tessier ,  Yun-Yu Wang ,  Daewon Yang ,  Chienfan Yu

IPC: H01L27/088 ,  H01L21/3205

CPC classification number: H01L21/823807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76837 ,  H01L21/823864 ,  H01L29/7843

Abstract: A method of fabricating a gate structure in a metal oxide semiconductor field effect transistor (MOSFET) and the structure thereof is provided. The MOSFET may be n-doped or p-doped. The gate structure, disposed on a substrate, includes a plurality of gates. Each of the plurality of gates is separated by a vertical space from an adjacent gate. The method deposits at least one dual-layer liner over the gate structure filling each vertical space. The dual-layer liner includes at least two thin high density plasma (HDP) films. The deposition of both HDP films occurs in a single HDP chemical vapor deposition (CVD) process. The dual-layer liner has properties conducive for coupling with plasma enhanced chemical vapor deposition (PECVD) films to form tri-layer or quadric-layer film stacks in the gate structure.

Abstract translation: 提供了在金属氧化物半导体场效应晶体管（MOSFET）中制造栅极结构的方法及其结构。 MOSFET可以是n掺杂或p掺杂的。 设置在基板上的栅极结构包括多个栅极。 多个栅极中的每一个与相邻栅极分开一垂直空间。 该方法将填充每个垂直空间的至少一个双层衬垫沉积在栅极结构上。 双层衬垫包括至少两个薄的高密度等离子体（HDP）膜。 两种HDP膜的沉积在单个HDP化学气相沉积（CVD）工艺中发生。 双层衬垫具有有利于与等离子体增强化学气相沉积（PECVD）膜耦合以在栅极结构中形成三层或二次层膜堆叠的性质。

公开(公告)号：US07491660B2

公开(公告)日：2009-02-17

申请号：US11873721

申请日：2007-10-17

Applicant: Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

Inventor： Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

IPC: H01L21/31 ,  H01L21/469 ,  C23C16/00 ,  C23C14/10 ,  C23C14/00

CPC classification number: H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

Abstract translation: 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

公开(公告)号：US07462527B2

公开(公告)日：2008-12-09

申请号：US11160705

申请日：2005-07-06

Applicant: Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

Inventor： Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

Abstract translation: 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

公开(公告)号：US20080286545A1

公开(公告)日：2008-11-20

申请号：US12145922

申请日：2008-06-25

Applicant: Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

Inventor： Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

IPC: B32B7/02

CPC classification number: H01L21/26513 ,  H01L21/266 ,  Y10T428/24992

Abstract: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.

Abstract translation: 形成用于植入衬底的掩模和使用具有光刻胶的注入阻挡层进行植入的方法提供了较低的纵横比掩模，其在去除掩模期间对衬底中的沟槽隔离造成最小的损害。 在一个实施例中，形成掩模的方法包括：在衬底上沉积注入阻挡层; 在所述注入阻挡层上沉积光致抗蚀剂，所述注入阻挡层的密度大于所述光致抗蚀剂; 通过去除光致抗蚀剂的一部分以暴露植入物停止层，在光致抗蚀剂中形成图案; 并通过蚀刻将图案转移到植入物停止层中以形成掩模。 注入停止层可以包括：氢化碳化锗，氮化碳化锗，氟化锗碳化物和/或无定形锗碳氢化物（GeHX），其中X包括碳。 方法/掩模减少了植入过程中的散射，因为掩模具有比常规掩模更高的密度。

公开(公告)号：US07372158B2

公开(公告)日：2008-05-13

申请号：US11467593

申请日：2006-08-28

Applicant: Yun-Yu Wang ,  Richard A Conti ,  Chung-Ping Eng ,  Matthew C Nicholls

Inventor： Yun-Yu Wang ,  Richard A Conti ,  Chung-Ping Eng ,  Matthew C Nicholls

IPC: H01L29/40

CPC classification number: H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.

Abstract translation: 一种覆盖氮化物叠层，可以防止蚀刻渗透到HDP氮化物，同时保持在Cu顶部的HDP氮化物的电迁移效果。 在一个实施例中，堆叠包括第一层HDP氮化物和设置在第一层上的Si-C-H化合物的第二层。 Si-C-H化合物例如是BLoK或N-BLoK（Si-C-H-N），并且选自在通孔RIE期间具有高选择性的一组材料，使得来自下一个布线层的RIE化学不会穿透。 碳氮是关键要素。 在另一个实施例中，堆叠包括第一层HDP氮化物，随后是第二层UVN（等离子体氮化物），以及包含设置在第二层上的HDP氮化物的第三层。

公开(公告)号：US07179760B2

公开(公告)日：2007-02-20

申请号：US10908833

申请日：2005-05-27

Applicant: Richard A. Conti ,  Thomas F. Houghton ,  Michael F. Lofaro ,  Jeffery B. Maxson ,  Ann H. McDonald ,  Yun-Yu Wang ,  Keith Kwong Hon Wong ,  Daewon Yang

Inventor： Richard A. Conti ,  Thomas F. Houghton ,  Michael F. Lofaro ,  Jeffery B. Maxson ,  Ann H. McDonald ,  Yun-Yu Wang ,  Keith Kwong Hon Wong ,  Daewon Yang

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L23/53238 ,  H01L21/28556 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a bilayer cap structure for interconnect structures that comprise copper metallization or other conductive metallization. Such bilayer cap structure includes a first cap layer formed by an unbiased high density plasma (HDP) chemical vapor deposition process, and a second cap layer over the first cap layer, where the second cap layer is formed by a biased high density plasma (bHDP) chemical vapor deposition process. During the bHDP chemical vapor deposition process, a low AC bias power is applied to the substrate to increase the ion bombardment on the substrate surface and to induce resputtering of the capping material, thereby forming a seamless second cap layer with excellent reactive ion etching (RIE) selectivity.

Abstract translation: 本发明涉及一种用于互连结构的双层盖结构，其包括铜金属化或其它导电金属化。 这种双层盖结构包括通过无偏高密度等离子体（HDP）化学气相沉积工艺形成的第一盖层和在第一盖层上的第二盖层，其中第二盖层由偏置的高密度等离子体（bHDP ）化学气相沉积工艺。 在bHDP化学气相沉积工艺期间，将低AC偏置功率施加到衬底上以增加衬底表面上的离子轰击并引起封盖材料的再溅射，从而形成具有优异的反应离子蚀刻（RIE）的无缝第二帽层 ）选择性。