公开(公告)号：US11921834B2

公开(公告)日：2024-03-05

申请号：US16249804

申请日：2019-01-16

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Fabrice Marinet

IPC: G06F21/00 ,  B41J2/175 ,  G06F21/44 ,  G06K15/02 ,  G06F21/73

CPC classification number: G06F21/44 ,  B41J2/17546 ,  B41J2/17566 ,  G06K15/1822 ,  G06F21/73 ,  G06F2221/2129

Abstract: A method of authenticating a first electronic circuit includes generating a first signature using the first electronic circuit, the generating of the first signature being based on states of a plurality of electric nodes distributed within the first electronic circuit. A second signature is generated using a second electronic circuit, the generating of the second signature being based on states of a plurality of electric nodes distributed within the second electronic circuit. The first signature is compared to the second signature. The first electronic circuit is authenticated based on the comparison of the first signature to the second signature.

公开(公告)号：US11894657B2

公开(公告)日：2024-02-06

申请号：US17360381

申请日：2021-06-28

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： Romeo Letor ,  Vanni Poletto ,  Antoine Pavlin ,  Nadia Lecci ,  Alfio Russo

IPC: H01S5/062 ,  H03K5/07 ,  H01S5/026

CPC classification number: H01S5/06216 ,  H01S5/0261 ,  H03K5/07

Abstract: An embodiment pulse generator circuit comprises a first electronic switch coupled between first and second nodes, and a second electronic switch coupled between the second node and a reference node. An LC resonant circuit comprising an inductance and a capacitance is coupled between the first and reference nodes along with charge circuitry comprises a further inductance in a current flow line between a supply node and an intermediate node in the LC resonant circuit. Drive circuitry of the electronic switches repeats, during a sequence of switching cycles, charge time intervals, wherein the capacitance in the LC resonant circuit is charged via the charge circuit, and pulse generation time intervals, wherein a pulsed current is provided to the load via the first and second nodes. The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit oscillates at a resonance frequency.

公开(公告)号：US11889397B2

公开(公告)日：2024-01-30

申请号：US17649146

申请日：2022-01-27

Applicant: STMicroelectronics (Rousset) SAS ,  STMICROELECTRONICS GMBH

Inventor： Thierry Meziache ,  Pierre Rizzo ,  Alexandre Charles ,  Juergen Boehler

IPC: H04W4/80 ,  G06K7/00 ,  G06K7/10 ,  H04B5/00

CPC classification number: H04W4/80 ,  G06K7/0008 ,  G06K7/10237 ,  G06K7/10247 ,  H04B5/0031

Abstract: A device, including a main element and a set of at least two auxiliary elements, said main element including a master SWP interface, each auxiliary element including a slave SWP interface connected to said master SWP interface of said NFC element through a controllably switchable SWP link and management means configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

公开(公告)号：US11855633B2

公开(公告)日：2023-12-26

申请号：US17827515

申请日：2022-05-27

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jean-Francois Link ,  Mark Wallis ,  Joran Pantel

IPC: H03K19/17724 ,  H03K19/173 ,  H03K19/17704 ,  H03K3/0233 ,  H03K19/096

CPC classification number: H03K19/17724 ,  H03K3/0233 ,  H03K19/096 ,  H03K19/1737 ,  H03K19/17708

Abstract: An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.

公开(公告)号：US20230401306A1

公开(公告)日：2023-12-14

申请号：US18207292

申请日：2023-06-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Laurent TABARIES

IPC: G06F21/44 ,  G06F21/78

CPC classification number: G06F21/44 ,  G06F21/78

Abstract: The electronic control unit includes a communication circuit adapted to receive intelligent transport system messages, an authentication circuit designed to authenticate the received messages, a non-volatile memory configured to record the authenticated received messages, and a secure element. The secure element includes a blacklist of automatically excluded senders and is configured to directly reject a received message from a sender on the blacklist without authentication using the authentication circuit. Alternatively, the secure element includes a whitelist of automatically allowed senders and is configured to directly record a received message from a sender on the whitelist in the non-volatile memory without authentication using the authentication circuit.

公开(公告)号：US11838024B2

公开(公告)日：2023-12-05

申请号：US17119865

申请日：2020-12-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Tramoni ,  Jimmy Fort

IPC: H03K3/0233 ,  G06F1/3287 ,  H03K17/687

CPC classification number: H03K3/02337 ,  G06F1/3287 ,  H03K17/687

Abstract: An embodiment provides a circuit of cyclic activation of an electronic function including a hysteresis comparator controlling the charge of a capacitive element powering the function.

公开(公告)号：US11818883B2

公开(公告)日：2023-11-14

申请号：US17540029

申请日：2021-12-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart ,  Benoit Froment

IPC: H10B20/00 ,  H01L23/00 ,  G11C16/04

CPC classification number: H10B20/367 ,  G11C16/0466 ,  H01L23/57

Abstract: The present description concerns a ROM including at least one first rewritable memory cell.

公开(公告)号：US20230359368A1

公开(公告)日：2023-11-09

申请号：US18192237

申请日：2023-03-29

Applicant: STMicroelectronics(Rousset) SAS

Inventor： Mark Wallis ,  Laurent Lestringand

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/0673

Abstract: In accordance with an embodiment, a system-on-chip includes: a memory circuit comprising a first memory region accessible with a first access right level and a second memory region accessible with the first access right level or a second access right level, at least one first peripheral having the first access right level, at least one second peripheral having the second access right level; and a direct memory access circuit configured to generate direct memory accesses, wherein the direct memory access circuit includes at least one first direct memory access controller having the first access right level and at least one second direct memory access controller having the second access right level.

公开(公告)号：US11804842B2

公开(公告)日：2023-10-31

申请号：US17846362

申请日：2022-06-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Borrel ,  Jimmy Fort ,  Mathieu Lisart

IPC: H03K5/22 ,  H03K19/003 ,  H03F3/45 ,  H03K19/00 ,  H03K19/17736 ,  H03L7/097 ,  H04L9/32

CPC classification number: H03K19/00384 ,  H03F3/45273 ,  H03F3/45488 ,  H03K19/0027 ,  H03K19/17744 ,  H03L7/097 ,  H04L9/3278 ,  H04L2209/12

Abstract: A physically unclonable function device includes a set of diode-connected MOS transistors having a random distribution of respective threshold voltages. A first circuit is configured to impose, on each first transistor, a fixed respective gate voltage regardless of the value of a current flowing in this first transistor. A second circuit is configured to impose, on each second transistor, a fixed respective gate voltage regardless of the value of a current flowing in this second transistor. A current mirror stage is coupled between the first circuit and the second circuit and is configured to deliver the reference current from a sum of the currents flowing in the first transistors. A comparator is configured to deliver a signal whose level depends on a comparison between a first current obtained from a reference current based on the first transistors and a second current of the second transistors.

公开(公告)号：US11800821B2

公开(公告)日：2023-10-24

申请号：US17856711

申请日：2022-07-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin ,  Daniel Benoit ,  Remy Berthelon

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/30 ,  H10N70/021 ,  H10N70/826

Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.