公开(公告)号：US07582394B2

公开(公告)日：2009-09-01

申请号：US10957599

申请日：2004-10-05

Applicant: Kenji Noda ,  Shin Hashimoto

Inventor： Kenji Noda ,  Shin Hashimoto

IPC: G03F1/00 ,  H01L21/00

CPC classification number: G03F1/36

Abstract: A photomask includes, on a translucent substrate, three or more first light-shielding portions each in insular shape having a property of shielding exposure light and spaced equidistantly, a second light-shielding portion having a property of shielding the exposure light and formed to connect the adjacent first light-shielding portions, and first light-transmitting portions each in slit shape having a property of transmitting the exposure light and formed to be surrounded with the first and second light-shielding portions. The second light-shielding portion is formed to contain a point located equidistantly from the three or more first light-shielding portions.

Abstract translation: 一种光掩模在透光性基板上具有三个以上的具有隔离曝光光等间隔的特性的具有岛状的三个以上的第一遮光部，具有屏蔽曝光光的特性的第二遮光部，形成为连接 相邻的第一遮光部和具有透射曝光光的特性的狭缝状的第一透光部，形成为被第一和第二遮光部包围。 第二遮光部形成为包含与三个以上的第一遮光部等距离地设置的点。

公开(公告)号：US20090194796A1

公开(公告)日：2009-08-06

申请号：US11569798

申请日：2006-03-01

Applicant: Shin Hashimoto ,  Makoto Kiyama ,  Tatsuya Tanabe ,  Kouhei Miura ,  Takashi Sakurada

Inventor： Shin Hashimoto ,  Makoto Kiyama ,  Tatsuya Tanabe ,  Kouhei Miura ,  Takashi Sakurada

IPC: H01L29/812 ,  H01L29/78 ,  H01L29/207

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/2003 ,  H01L29/8611 ,  H01L29/872

Abstract: Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm−3 or more. The donor impurity is at least either silicon or germanium.

Abstract translation: 提供具有其中可以在n型氮化镓衬底上提供具有期望的低载流子浓度的n型氮化镓膜的结构的垂直氮化镓半导体器件的外延衬底。 氮化镓外延膜（65）设置在氮化镓衬底（63）上。 在氮化镓衬底（63）和氮化镓外延膜（65）中设置一个层区（67）。 氮化镓衬底（43）和氮化镓外延膜（65）之间的界面位于层区（67）中。 在层区域（67）中，施主杂质沿着氮化镓衬底（63）到氮化镓外延膜（65）的轴的峰值为1×10 18 cm -3以上。 供体杂质至少是硅或锗。

公开(公告)号：US20090189190A1

公开(公告)日：2009-07-30

申请号：US11571156

申请日：2006-03-03

Applicant: Shin Hashimoto ,  Makoto Kiyama ,  Takashi Sakurada ,  Tatsuya Tanabe ,  Kouhei Miura ,  Tomihito Miyazaki

Inventor： Shin Hashimoto ,  Makoto Kiyama ,  Takashi Sakurada ,  Tatsuya Tanabe ,  Kouhei Miura ,  Tomihito Miyazaki

IPC: H01L29/80 ,  H01L21/20

CPC classification number: H01L29/7787 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/66462

Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm−3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm−3.

Abstract translation: 提供具有高纯度沟道层和高电阻缓冲层的高电子迁移率晶体管。 高电子迁移率晶体管11设置有由氮化镓构成的支撑基板13，由第一氮化镓半导体构成的缓冲层15，由第二氮化镓半导体构成的沟道层17，由第三氮化镓半导体构成的半导体层19 氮化镓半导体，以及用于晶体管11的电极结构（栅电极21，源电极23和漏电极25）。第三氮化镓半导体的带隙比第二氮化镓半导体的带隙宽。 第一氮化镓半导体的碳浓度NC1为4×10 17 cm -3以上。 第二氮化镓半导体的碳浓度NC2小于4×10 16 cm -3。

公开(公告)号：US07538005B2

公开(公告)日：2009-05-26

申请号：US11714195

申请日：2007-03-06

Applicant: Kyoko Egashira ,  Shin Hashimoto

Inventor： Kyoko Egashira ,  Shin Hashimoto

IPC: H01L21/20

CPC classification number: H01L28/60 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive film, a dielectric film formed on the lower capacitor electrode, and an upper capacitor electrode made of the second conductive film and formed on the dielectric film.

Abstract translation: 半导体器件由以下部分构成：由第一导电膜和第二导电膜构成的互连，其从形成在基板上的绝缘膜上的互连下侧依次层叠; 以及由第一导电膜制成的下部电容电极，形成在下部电容电极上的电介质膜和形成在该电介质膜上的由上述第二导电膜构成的上部电容电极构成的电容器。

公开(公告)号：US20070155147A1

公开(公告)日：2007-07-05

申请号：US11714195

申请日：2007-03-06

Applicant: Kyoko Egashira ,  Shin Hashimoto

Inventor： Kyoko Egashira ,  Shin Hashimoto

IPC: H01L21/3205

CPC classification number: H01L28/60 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive film, a dielectric film formed on the lower capacitor electrode, and an upper capacitor electrode made of the second conductive film and formed on the dielectric film.

Abstract translation: 半导体器件由以下部分构成：由第一导电膜和第二导电膜构成的互连，其从形成在基板上的绝缘膜上的互连下侧依次堆叠; 以及由第一导电膜制成的下部电容电极，形成在下部电容电极上的电介质膜和形成在该电介质膜上的由上述第二导电膜构成的上部电容电极构成的电容器。

公开(公告)号：US07037371B1

公开(公告)日：2006-05-02

申请号：US09856823

申请日：2000-10-03

Applicant: Shin Hashimoto ,  Takenobu Kishida ,  Kyoko Egashira ,  Yoshifumi Hata ,  Toru Nishiwaki ,  Tomoya Tanaka

Inventor： Shin Hashimoto ,  Takenobu Kishida ,  Kyoko Egashira ,  Yoshifumi Hata ,  Toru Nishiwaki ,  Tomoya Tanaka

IPC: H01L21/28

CPC classification number: H01L21/26506 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S148/019 ,  Y10S148/046

Abstract: After distributing a nonmetal element in a region in the vicinity of a surface portion of a semiconductor layer, a metal film is deposited on the semiconductor layer. Next, a semiconductor-metal compound layer is epitaxially grown in the surface portion of the semiconductor layer by causing a reaction between an element included in the semiconductor layer and a metal included in the metal film through annealing carried out on the metal film.

Abstract translation: 在半导体层的表面部分附近的区域中分布非金属元素之后，在半导体层上沉积金属膜。 接下来，通过在金属膜上进行退火，通过在半导体层中包含的元素与包含在金属膜中的金属之间的反应而在半导体层的表面部分中外延生长半导体 - 金属化合物层。

公开(公告)号：US06585560B2

公开(公告)日：2003-07-01

申请号：US09731011

申请日：2000-12-07

Applicant: Akihiro Tanoue ,  Yoshiharu Hidaka ,  Shin Hashimoto

Inventor： Akihiro Tanoue ,  Yoshiharu Hidaka ,  Shin Hashimoto

IPC: B24B100

CPC classification number: B24B37/04 ,  B24B57/02

Abstract: A slurry feeding apparatus includes closed slurry bottle, piping, wet nitrogen generator, wet nitrogen supply pipe, suction and spray nozzles, temperature regulator, flow rate control valves, slurry delivery pump and controller for controlling the operation and flow rate of the slurry delivery pump. While a wafer is being polished by a CMP polisher, the controller continuously operates the pump. On the other hand, while the polisher is idling, the controller starts and stops the pump intermittently at regular intervals. No stirrer like a propeller is inserted into the slurry bottle, but the slurry is stirred up by spraying the slurry through the spray nozzle.

公开(公告)号：US6005401A

公开(公告)日：1999-12-21

申请号：US837954

申请日：1997-04-14

Applicant: Yoshirou Nakata ,  Toshio Yamada ,  Atsushi Fujiwara ,  Isao Miyanaga ,  Shin Hashimoto ,  Yukiharu Uraoka ,  Yasushi Okuda ,  Kenzou Hatada

Inventor： Yoshirou Nakata ,  Toshio Yamada ,  Atsushi Fujiwara ,  Isao Miyanaga ,  Shin Hashimoto ,  Yukiharu Uraoka ,  Yasushi Okuda ,  Kenzou Hatada

IPC: G01R1/04 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66

CPC classification number: G01R31/2886 ,  G01R1/0491 ,  G01R31/2867 ,  G01R31/2831

Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

Abstract translation: 提供了一种保持板，其具有多个用于测试半导体芯片的集成电路端子的半导体晶片，与具有电连接到其相应的集成电路端子的多个探针端子的探针片相对。 具有与多个探针端子电连接的布线的绝缘基板设置在与保持板相对的探针片上。 在探针片和绝缘基片之间插入弹性部件。 保持板和探针片的关系使得由保持板保持的半导体晶片的每个集成电路端子电连接到其对应的探针片的探针端子。

公开(公告)号：US5645628A

公开(公告)日：1997-07-08

申请号：US502175

申请日：1995-07-13

Applicant: Masayuki Endo ,  Akemi Kawaguchi ,  Mikio Nishio ,  Shin Hashimoto

Inventor： Masayuki Endo ,  Akemi Kawaguchi ,  Mikio Nishio ,  Shin Hashimoto

IPC: C23C18/34 ,  C23C18/40 ,  C23C18/44 ,  C23C18/31

CPC classification number: C23C18/40 ,  C23C18/34 ,  C23C18/44

Abstract: A contact hole and a wiring groove are formed in an insulating layer formed on a semiconductor substrate. A silver layer is formed inside of the contact hole and the wiring groove and on the insulating layer with the use of an electroless plating bath comprising: silver nitrate containing silver ions; tartaric acid serving as a reducing agent of the silver ions; ethylenediamine serving as a complexing agent of the silver ions; and metallic ions of tetramethylammoniumhydroxide serving as a pH control agent. Then, the silver layer on the insulating layer is removed by a chemical and mechanical polishing method such that an embedded wiring is formed in each of the contact hole and the wiring groove.

Abstract translation: 在半导体衬底上形成的绝缘层中形成接触孔和布线槽。 通过使用含有银离子的硝酸银的化学镀浴，在接触孔和布线槽内部和绝缘层上形成银层; 酒石酸作为银离子的还原剂; 乙二胺作为银离子的络合剂; 和作为pH调节剂的四甲基氢氧化铵的金属离子。 然后，通过化学和机械抛光方法去除绝缘层上的银层，使得在每个接触孔和布线槽中形成嵌入的布线。

公开(公告)号：US5455205A

公开(公告)日：1995-10-03

申请号：US34763

申请日：1993-03-19

Applicant: Hiroyuki Umimoto ,  Shin Hashimoto ,  Shinji Odanaka

Inventor： Hiroyuki Umimoto ,  Shin Hashimoto ,  Shinji Odanaka

IPC: H01L21/3105 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/02

CPC classification number: H01L27/10852 ,  H01L21/3105 ,  H01L27/108 ,  H01L27/105 ,  Y10S148/133 ,  Y10S438/978

Abstract: There is disclosed a method of producing a semiconductor memory device. An interlayer insulation film is formed on a semiconductor substrate including a switching transistor. Then, a memory node pattern reaching an active region of the switching transistor is formed. A cell plate electrode pattern is formed through an insulation film formed on the memory node in such a manner that a value obtained by subtracting a thickness of a polycrystalline silicon film for a cell plate electrode from an overlapping dimension of a memory node pattern and the cell plate electrode pattern is not less than two times larger and not more than ten times larger than a thickness of deposition of a BPSG film. Then, the BPSG film is deposited on an entire surface, and then is caused to viscously flow by a heat treatment. Then, an aluminum wiring is formed on the BPSG film. With this construction, a step of the aluminum wiring in a boundary region between a memory cell array portion and a peripheral circuit portion, or in a word line-backing contact forming region, is decreased, thereby preventing the lowering of the yield of the aluminum wiring which is caused by the cutting of the aluminum wiring and the remaining of a residue of etching for a contact-forming electrode (for example, tungsten).

Abstract translation: 公开了一种制造半导体存储器件的方法。 在包括开关晶体管的半导体衬底上形成层间绝缘膜。 然后，形成到达开关晶体管的有源区的存储器节点图形。 通过形成在存储节点上的绝缘膜形成单元板电极图案，使得通过从存储器节点图案和单元的重叠尺寸减去用于单元板电极的多晶硅膜的厚度而获得的值 平板电极图案不小于BPSG膜的沉积厚度的两倍以上且不大于十倍。 然后，将BPSG膜沉积在整个表面上，然后通过热处理使其粘稠流动。 然后，在BPSG膜上形成铝布线。 利用这种结构，在存储单元阵列部分和外围电路部分之间或字线 - 背衬接触形成区域中的边界区域中的铝布线的步骤减小，从而防止铝的收率降低 通过切割铝布线引起的布线和剩余的用于接触形成电极（例如钨）的蚀刻残留物。