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    Register integrity check in configurable devices
    21.
    发明授权
    Register integrity check in configurable devices 有权

    公开(公告)号：US12124323B2

    公开(公告)日：2024-10-22

    申请号：US17883379

    申请日：2022-08-08

    Applicant: XILINX, INC.

    Inventor： Ahmad R. Ansari ,  David P. Schultz ,  Felix Burton ,  Jeffrey Cuppett

    IPC: G06F11/07 ,  G06F9/30

    CPC classification number: G06F11/0763 ,  G06F9/30101 ,  G06F11/0772

    Abstract: Embodiments herein describe integrity check techniques that are efficient and flexible by using local registers in a segment to store check values which can be used to detect errors in the local configuration data in the same segment. In addition to containing local registers storing the check values, each segment can include a mask register indicated which of the configuration registers should be checked and which can be ignored. Further, the segments can include a next segment register indicating the next segment the check engine should evaluate for errors.

    ALIGNING MULTI-CHIP DEVICES
    22.
    发明公开
    ALIGNING MULTI-CHIP DEVICES 审中-公开

    公开(公告)号：US20240346220A1

    公开(公告)日：2024-10-17

    申请号：US18134497

    申请日：2023-04-13

    Applicant: XILINX, INC.

    Inventor： Martin L. VOOGEL

    IPC: G06F30/347

    CPC classification number: G06F30/347

    Abstract: Embodiments herein describe arranging TX and RX circuitry in ICs such that rotated and mirrored ICs are aligned when connected in a multiple-chip device. In one embodiment, the TX circuitry (e.g., TX physical layer or PHY) is arranged in one row while the RX circuitry (e.g., RX physical layer or PHY) is arranged in another row. As such, when an IC is rotated or mirrored, at least one TX PHY is aligned with a RX PHY on the other IC. As such, non-crossing chip-to-chip connections can be formed through the interposer.

    NETWORK INTERFACE DEVICE
    23.
    发明公开
    NETWORK INTERFACE DEVICE 审中-公开

    公开(公告)号：US20240345979A1

    公开(公告)日：2024-10-17

    申请号：US18642714

    申请日：2024-04-22

    Applicant: XILINX, INC.

    Inventor： Steven Leslie POPE ,  Derek Edward ROBERTS ,  Dmitri KITARIEV ,  Neil Duncan TURTON ,  David James RIDDOCH ,  Ripduman SOHAN

    IPC: G06F13/40 ,  G06F9/48

    CPC classification number: G06F13/4068 ,  G06F9/4881

    Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.

    LOW LATENCY PHASE ALIGNMENT FOR PARALLEL DATA PATHS
    24.
    发明公开
    LOW LATENCY PHASE ALIGNMENT FOR PARALLEL DATA PATHS 审中-公开

    公开(公告)号：US20240333270A1

    公开(公告)日：2024-10-03

    申请号：US18128945

    申请日：2023-03-30

    Applicant: XILINX, INC.

    Inventor： Riyas Noorudeen REMLA ,  Showi-Min SHEN

    IPC: H03K5/01

    CPC classification number: H03K5/01 ,  H03K2005/00078 ,  H03K2005/00286

    Abstract: Receiver circuitry for mitigating effects associated with the phase differences between a capture clock signal and the receipt of a data signal includes first data path circuitry, second data path circuitry, and phase alignment circuitry. The first data path circuitry receives a first data signal based on a capture clock signal. The second data path circuitry receives a second data signal based on the capture clock signal. The phase alignment circuitry adjusts the phase of a first launch clock signal and a second launch clock signal based on a first clock slip signal and a second clock slip signal, respectively. The phase alignment circuitry adjusts a phase of the capture clock signal relative to one of the first and the second launch clock signals based on a first adjustment value associated with the first data path circuitry and a second adjustment value associated with the second data path circuitry.

    CONTROL SET OPTIMIZATION FOR IMPLEMENTING CIRCUIT DESIGNS IN INTEGRATED CIRCUIT DEVICES
    25.
    发明公开
    CONTROL SET OPTIMIZATION FOR IMPLEMENTING CIRCUIT DESIGNS IN INTEGRATED CIRCUIT DEVICES 审中-公开

    公开(公告)号：US20240330558A1

    公开(公告)日：2024-10-03

    申请号：US18193197

    申请日：2023-03-30

    Applicant: Xilinx, Inc.

    Inventor： Jichun Wang ,  Wuxi Li ,  Chun Zhang ,  Paul Kundarewich ,  John Blaine

    IPC: G06F30/392

    CPC classification number: G06F30/392

    Abstract: Implementing circuit designs in integrated circuit devices includes determining, using computer hardware, regular control sets, super control sets, and mega control sets for a circuit design. Control set optimization is performed on the circuit design. Performing control set optimization includes performing a clock-enable-only control set reduction for each super control set. Performing control set optimization includes performing a set/reset control set reduction and a clock-enable control set reduction for each mega control set. The circuit design is selectively modified by committing changes determined from the control set reductions to the circuit design on a per control set basis based on an improvement of a cost metric for each control set.

    High-speed communication between integrated circuits of an emulation system
    27.
    发明授权
    High-speed communication between integrated circuits of an emulation system 有权

    公开(公告)号：US12099790B1

    公开(公告)日：2024-09-24

    申请号：US17204431

    申请日：2021-03-17

    Applicant: Xilinx, Inc.

    Inventor： Raghukul B. Dikshit ,  Tauheed Ashraf ,  Michael Chyziak

    IPC: G06F30/331 ,  H04J3/06

    CPC classification number: G06F30/331 ,  H04J3/06

    Abstract: An emulation system can include a first integrated circuit (IC) including first circuitry and a first transceiver. The first circuitry is configured to emulate a first partition of a circuit design. The first circuitry is clocked by an emulation clock and the first transceiver is clocked by a transceiver clock asynchronous with the emulation clock. The transceiver clock has a higher frequency than the emulation clock. The emulation system can include a second IC configured to emulate a second partition of the circuit design. The second IC includes a second transceiver. The first transceiver is configured to generate multiplexed emulation data by multiplexing a plurality of nets that cross from the first partition to the second partition of the circuit design. The first transceiver is configured to send the multiplexed emulation data over a serial communication channel to the second transceiver. The multiplexed emulation data includes a clock signal of the first transceiver embedded therein.

    Registration of a PUF signature and regeneration using a trellis decoder
    29.
    发明授权
    Registration of a PUF signature and regeneration using a trellis decoder 有权

    公开(公告)号：US12081238B2

    公开(公告)日：2024-09-03

    申请号：US18084974

    申请日：2022-12-20

    Applicant: Xilinx, Inc.

    Inventor： James Wesselkamper

    IPC: H03M13/25 ,  H03M13/11

    CPC classification number: H03M13/256 ,  H03M13/1111

    Abstract: A physically unclonable function includes a circuit that translates a normally distributed sequence of raw sample into a sequence of uniformly distributed binned values across sub-bins of bins. Helper circuitry generates centering values and parity bits based on binned values generated during registration. Each centering value is associated with a raw sample value corresponding to a binned value and indicates an offset of a sub-bin in one of the bins. A distance calculator generates a set of distances from each raw sample value based on the centering value associated with the raw sample value. Each distance indicates a difference between the respective raw sample value and a raw sample value equivalent to a midpoint of a sub-bin offset by the associated centering value in a bin. A trellis decoder generates a PUF signature based on the candidate symbols, sets of distances, and parity bits.

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