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公开(公告)号：US07638387B2
公开(公告)日：2009-12-29
申请号：US11823381
申请日：2007-06-27
Applicant: Yong-Kyu Lee , Hee-Seog Jeon , Jeong-Uk Han , Young-Ho Kim , Myung-Jo Chun
Inventor： Yong-Kyu Lee , Hee-Seog Jeon , Jeong-Uk Han , Young-Ho Kim , Myung-Jo Chun
IPC: H01L21/8234
CPC classification number: H01L27/1021
Abstract: A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.
Abstract translation: 掩模只读存储器（ROM）包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。 在第一导线中形成多个二极管，并且为第一组二极管形成多个最终通孔，每个二极管表示第一类型的存储单元，没有形成用于第二组二极管的最终通孔，每个二极管表示 第二种类型的存储单元。 多个第二导电线中的每一个形成在二极管的列上。
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公开(公告)号：US20090065850A1
公开(公告)日：2009-03-12
申请号：US12266201
申请日：2008-11-06
Applicant: Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Yong-Kyu Lee
Inventor： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Yong-Kyu Lee
IPC: H01L29/792
CPC classification number: H01L29/785 , B82Y10/00 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L29/78645
Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.
Abstract translation: 根据本发明的具有多栅极结构的非易失性存储器件及其形成方法，使用镶嵌工艺形成栅电极。 因此，在用于形成栅电极的工艺中，电荷存储层，隧道绝缘层，阻挡绝缘层和栅极电极层不会被蚀刻侵蚀，从而形成具有良好可靠性的非易失性存储器件。
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公开(公告)号：US20090004118A1
公开(公告)日：2009-01-01
申请号：US11664886
申请日：2005-10-07
Applicant: Shuming Nie , Yong Kyu Lee , Gloria Kim
Inventor： Shuming Nie , Yong Kyu Lee , Gloria Kim
CPC classification number: A61K49/0002 , A61K47/547 , A61K47/551 , A61K47/61 , A61K47/645 , A61K47/6849 , A61K47/6939 , B82Y5/00
Abstract: Disclosed herein are conjugates comprising a nanocarrier, a therapeutic agent or imaging agent and a targeting agent. Also disclosed herein are compositions comprising such conjugates and methods for using the conjugates to deliver therapeutic and/or imaging agents to cells. Also disclosed are methods for using the conjugates to treat particular disorders, such as proliferative disorders.
Abstract translation: 本文公开了包含纳米载体，治疗剂或成像剂和靶向剂的缀合物。 本文还公开了包含这种缀合物的组合物和使用缀合物将治疗和/或成像剂递送至细胞的方法。 还公开了使用缀合物来治疗特定疾病如增殖性疾病的方法。
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公开(公告)号：US07402493B2
公开(公告)日：2008-07-22
申请号：US11602032
申请日：2006-11-20
Applicant: Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Yong-Kyu Lee
Inventor： Chang-Woo Oh , Dong-Gun Park , Dong-Won Kim , Yong-Kyu Lee
IPC: H01L21/336
CPC classification number: H01L29/785 , B82Y10/00 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L29/78645
Abstract: According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability.
Abstract translation: 根据本发明的具有多栅极结构的非易失性存储器件及其形成方法，使用镶嵌工艺形成栅电极。 因此，在用于形成栅电极的工艺中，电荷存储层，隧道绝缘层，阻挡绝缘层和栅极电极层不会被蚀刻侵蚀，从而形成具有良好可靠性的非易失性存储器件。
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25.发明授权Semiconductor device having a flash memory cell and fabrication method thereof 有权具有闪存单元的半导体器件及其制造方法公开(公告)号：US06784476B2
公开(公告)日：2004-08-31
申请号：US10039126
申请日：2002-01-03
Applicant: Dong-Jun Kim , Jin-Ho Kim , Yong-Kyu Lee , Min-Soo Cho , Eui-Youl Ryu
Inventor： Dong-Jun Kim , Jin-Ho Kim , Yong-Kyu Lee , Min-Soo Cho , Eui-Youl Ryu
IPC: H01L27108
CPC classification number: H01L27/11521 , H01L27/115 , H01L29/42328
Abstract: In a non-volatile semiconductor memory device and a fabrication method thereof, a charge storage layer is formed on a substrate. A control gate layer is formed on the charge storage layer. A gate mask having a spacer-shape is formed on the control gate layer. The charge storage layer and the control gate layer are removed using the gate mask as protection to form a control gate and a charge storage region.
Abstract translation: 在非易失性半导体存储器件及其制造方法中，在基板上形成电荷存储层。 在电荷存储层上形成控制栅极层。 在控制栅极层上形成具有间隔物形状的栅极掩模。 使用栅极掩模去除电荷存储层和控制栅极层作为保护以形成控制栅极和电荷存储区域。
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Patent Agency Ranking
公开(公告)号：US06724661B2
公开(公告)日：2004-04-20
申请号：US10090902
申请日：2002-05-31
Applicant: Yong-Kyu Lee , Dong-Jun Kim , Min-Soo Cho , Eui-Youl Ryu , Jin-Ho Kim
Inventor： Yong-Kyu Lee , Dong-Jun Kim , Min-Soo Cho , Eui-Youl Ryu , Jin-Ho Kim
IPC: G11C1604
CPC classification number: G11C16/14
Abstract: A method for performing an erase operation in a memory cell. A first voltage and a second voltage are applied to the source and drain regions, respectively, for a predetermined erase time; and the first and second voltages are switched with each other between the source and drain regions at least one time for the erase time. Thereby, hole is easily injected to the source and drain regions and a channel lateral surface, and a uniform and high-speed erase operation is archived.
Abstract translation: 一种在存储单元中执行擦除操作的方法。 分别在源极和漏极区域施加第一电压和第二电压达预定的擦除时间; 并且第一和第二电压在源极和漏极区之间彼此切换至少一次以用于擦除时间。 因此，孔容易地注入到源极和漏极区域以及沟道横向表面，并且存储均匀且高速的擦除操作。
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27.发明授权
公开(公告)号：US5903097A
公开(公告)日：1999-05-11
申请号：US998785
申请日：1997-12-29
Applicant: Yong-kyu Lee
Inventor： Yong-kyu Lee
CPC classification number: H01J9/261
Abstract: A method of manufacturing a side glass for a vacuum fluorescent display is provided wherein a glass is cut to a predetermined length in accordance with the size of the vacuum fluorescent display. The glass is then bent to coincide two ends of the glass in accordance with the shape of the vacuum fluorescent display, and the two ends of the glass are adhered to one another. A sealing frit is applied on the upper side of the glass, and is plasticized and cured.
Abstract translation: 提供一种制造用于真空荧光显示器的侧玻璃的方法，其中根据真空荧光显示器的尺寸将玻璃切割成预定长度。 然后根据真空荧光显示器的形状将玻璃弯曲以使玻璃的两端重合，玻璃的两端彼此粘合。 将密封玻璃料施加在玻璃的上侧，并且被塑化和固化。
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公开(公告)号：US09646687B2
公开(公告)日：2017-05-09
申请号：US14619992
申请日：2015-02-11
Applicant: Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyun-Kook Park
Inventor： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyun-Kook Park
CPC classification number: G11C13/0033 , G06F11/073 , G06F11/0751 , G06F11/0793 , G06F11/1048 , G11C13/0035 , G11C13/0069 , G11C29/52 , G11C2013/0092 , G11C2213/77
Abstract: Provided are a resistive memory device and an operating method for the resistive memory device. The operating method includes detecting a write cycle, determining whether or not to perform a recovery operation by comparing the detected write cycle with a first reference value, and upon determining to perform the recovery operation, performing the recovery operation on target memory cells of the memory cell array.
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公开(公告)号：US09570170B2
公开(公告)日：2017-02-14
申请号：US14839606
申请日：2015-08-28
Applicant: Chi-Weon Yoon , Hyun-Kook Park , Yeong-Taek Lee , Bo-Geun Kim , Yong-Kyu Lee
Inventor： Chi-Weon Yoon , Hyun-Kook Park , Yeong-Taek Lee , Bo-Geun Kim , Yong-Kyu Lee
CPC classification number: G11C13/0069 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C2213/72
Abstract: A memory device includes a memory cell array having multiple memory cells arranged respectively in regions where first signal lines cross second signal lines. The memory device further includes a decoder having multiple line selection switch units connected respectively to the of first signal lines. Each of the multiple line selection switch units applies a bias voltage to a first signal line corresponding to each of the multiple line selection switch units in response selectively to a first switching signal and a second switching signal, voltage levels of which are different from each other in activated states.
Abstract translation: 存储器件包括具有分别布置在第一信号线与第二信号线交叉的区域中的多个存储单元的存储单元阵列。 存储装置还包括具有分别连接到第一信号线的多个线路选择开关单元的解码器。 多个线路选择开关单元中的每一个选择性地响应于第一开关信号和彼此不同的第二开关信号的第一信号线施加偏置电压到对应于多个线路选择开关单元中的每一个的第一信号线 处于激活状态。
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公开(公告)号：US20160148683A1
公开(公告)日：2016-05-26
申请号：US14839606
申请日：2015-08-28
Applicant: CHI-WEON YOON , HYUN-KOOK PARK , YEONG-TAEK LEE , BO-GEUN KIM , YONG-KYU LEE
Inventor： CHI-WEON YOON , HYUN-KOOK PARK , YEONG-TAEK LEE , BO-GEUN KIM , YONG-KYU LEE
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C2213/72
Abstract: A memory device includes a memory cell array having multiple memory cells arranged respectively in regions where first signal lines cross second signal lines. The memory device further includes a decoder having multiple line selection switch units connected respectively to the of first signal lines. Each of the multiple line selection switch units applies a bias voltage to a first signal line corresponding to each of the multiple line selection switch units in response selectively to a first switching signal and a second switching signal, voltage levels of which are different from each other in activated states.
Abstract translation: 存储器件包括具有分别布置在第一信号线与第二信号线交叉的区域中的多个存储单元的存储单元阵列。 存储装置还包括具有分别连接到第一信号线的多个线路选择开关单元的解码器。 多个线路选择开关单元中的每一个选择性地响应于第一开关信号和彼此不同的第二开关信号的第一信号线施加偏置电压到对应于多个线路选择开关单元中的每一个的第一信号线 处于激活状态。
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