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    Fin field effect transistors having multi-layer fin patterns
    21.
    发明授权
    Fin field effect transistors having multi-layer fin patterns 失效
    鳍场效应晶体管具有多层翅片图案

    公开(公告)号：US07323710B2

    公开(公告)日：2008-01-29

    申请号：US10870743

    申请日：2004-06-17

    申请人： Young-Pil Kim ,  Sun-Ghil Lee ,  Si-Young Choi

    发明人： Young-Pil Kim ,  Sun-Ghil Lee ,  Si-Young Choi

    IPC分类号： H01L29/06 ,  H01L31/00

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

    摘要： A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that are greater than a lattice width of the substrate in at least one direction. In addition, the first and second semiconductor patterns may be alternately stacked to increase the height of the fin pattern, such that one of the first and second patterns can reduce stress from the other of the first and second patterns. The first and second semiconductor patterns may be formed of strained silicon and silicon-germanium, where the silicon-germanium patterns can reduce stress from the strained silicon patterns. Therefore, both the number of carriers and the mobility of carriers in the transistor channel may be increased, improving performance of the fin field effect transistor. Related methods are also discussed.

    摘要翻译： 鳍状场效应晶体管具有从半导体衬底突出的鳍状图案。 鳍状图案包括堆叠的第一半导体图案和第二半导体图案。 第一和第二半导体图案具有在至少一个方向上大于衬底的晶格宽度的晶格宽度。 此外，第一和第二半导体图案可以交替堆叠以增加鳍片图案的高度，使得第一和第二图案中的一个可以减小来自第一和第二图案中的另一个的应力。 第一和第二半导体图案可以由应变硅和硅 - 锗形成，其中硅 - 锗图案可以减小应变硅图案的应力。 因此，可以增加晶体管沟道中的载流子数和载流子的迁移率，从而提高鳍式场效应晶体管的性能。 还讨论了相关方法。

    Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors
    22.
    发明授权
    Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors 失效
    用于精确测量半导体单元晶体管中的漏电流的半导体器件测试图案和相关方法

    公开(公告)号：US07271408B2

    公开(公告)日：2007-09-18

    申请号：US10796672

    申请日：2004-03-09

    申请人： Young-pil Kim ,  Beom-jun Jin

    发明人： Young-pil Kim ,  Beom-jun Jin

    IPC分类号： H01L23/58

    CPC分类号： H01L27/10882 ,  H01L22/32 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor device test patterns are provided that include a word line on a semiconductor substrate and an active region having a first impurity doped region and a second impurity doped region in at the semiconductor substrate. A first self-aligned contact pad is electrically connected to the first impurity doped region, and a first direct contact is electrically connected to the first self-aligned contact pad. A first bit line is electrically connected to the first direct contact, and a first probing pad is electrically connected to the first bit line. The test pattern further includes a second self-aligned contact pad that is electrically connected to the second impurity doped region, and a second direct contact electrically connected to the second self-aligned contact pad. A second conductive line is electrically connected to the second direct contact, and a second probing pad is electrically connected to the second conductive line. These test patterns may be used to measure leakage current in a cell transistor of the semiconductor device.

    摘要翻译： 提供半导体器件测试图案，其包括在半导体衬底上的字线和在半导体衬底中具有第一杂质掺杂区和第二杂质掺杂区的有源区。 第一自对准接触焊盘电连接到第一杂质掺杂区域，第一直接接触电连接到第一自对准接触焊盘。 第一位线电连接到第一直接触点，并且第一探针焊盘电连接到第一位线。 测试图案还包括电连接到第二杂质掺杂区的第二自对准接触焊盘和电连接到第二自对准接触焊盘的第二直接接触。 第二导电线电连接到第二直接接触，第二探测焊盘电连接到第二导线。 这些测试图案可用于测量半导体器件的单元晶体管中的漏电流。

    Method of making a MOS transistor
    23.
    发明授权
    Method of making a MOS transistor 有权

    公开(公告)号：US06864178B1

    公开(公告)日：2005-03-08

    申请号：US10627059

    申请日：2003-07-25

    申请人： Young Pil Kim

    发明人： Young Pil Kim

    IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/336 ,  H01L21/461 ,  H01L29/49 ,  H01L29/76

    CPC分类号： H01L29/6653 ,  H01L21/28079 ,  H01L21/28097 ,  H01L29/495 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6659

    摘要： A method of making a MOS transistor is disclosed. The disclosed techniques can completely transform a polysilicon gate electrode into a metal silicide electrode through a brief thermal treatment process by extending the contact area between the polysilicide gate electrode and a metal layer prior to a formation of a metal silicide. The disclosed MOS transistor fabricating method comprises providing a semiconductor substrate further comprising a polysilicon gate electrode with a silicide layer thereon, a spacer, and source and drain regions with LDD regions; forming an insulating layer on the area of the substrate; polishing the insulating layer so that the top of the polysilicon gate electrode can be exposed; etching some part of the insulating layer and the spacer so that both lateral walls of the polysilicon gate electrode can be exposed; forming a metal layer on the substrate resulted from the preceding step so that the polysilicon gate electrode can be covered with the metal layer; and transforming completely the polysilicon gate electrode into a metal silicide gate electrode by performing a thermal treatment process.

    Semiconductor devices including elevated source and drain regions
    25.
    发明授权
    Semiconductor devices including elevated source and drain regions 有权
    半导体器件包括升高的源极和漏极区域

    公开(公告)号：US08552494B2

    公开(公告)日：2013-10-08

    申请号：US12962061

    申请日：2010-12-07

    申请人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    发明人： Jin-Bum Kim ,  Young-Pil Kim ,  Jung-Yun Won ,  Hion-Suck Baik ,  Jun-Ho Lee

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/66621

    摘要： Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.

    摘要翻译： 提供制造半导体器件的方法。 制备具有活性图案和隔离层图案的基板。 每个隔离层图案的上表面高于每个活动图案的上表面。 在基板上形成具有均匀厚度的间隔层。 蚀刻间隔层以在每个隔离层图案的侧壁上形成间隔物。 在每个有源图案上形成栅极结构。 对具有栅极结构的有源图案进行选择性外延生长（SEG）处理，以在活性图案上形成具有高于绝缘层图案的上表面的隔离的外延层。 还提供了相关的半导体器件。

    Bit line charge accumulation sensing for resistive changing memory
    29.
    发明授权
    Bit line charge accumulation sensing for resistive changing memory 有权
    电阻变化存储器的位线电荷累积检测

    公开(公告)号：US08203869B2

    公开(公告)日：2012-06-19

    申请号：US12326184

    申请日：2008-12-02

    申请人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    发明人： Chulmin Jung ,  Yong Lu ,  Kang Yong Kim ,  Young Pil Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C7/14 ,  G11C7/02 ,  G11C7/04 ,  G11C7/062 ,  G11C11/1673

    摘要： A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed.

    摘要翻译： 存储器阵列包括多个磁阻改变存储单元。 每个电阻变化存储单元在电源线和位线之间电连接，并且电阻在电阻变化存储单元和位线之间。 晶体管在源极区域和漏极区域之间具有电门，并且源极区域在电磁变化存储单元和栅极之间电连接。 字线电耦合到门。 还公开了用于磁阻改变存储器的位线电荷累积感测。