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    Memory hierarchy using row-based compression
    23.
    发明授权
    Memory hierarchy using row-based compression 有权
    使用基于行的压缩的内存层次结构

    公开(公告)号：US09477605B2

    公开(公告)日：2016-10-25

    申请号：US13939377

    申请日：2013-07-11

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gabriel H. Loh ,  James M. O'Connor

    IPC: G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/0866 ,  G06F12/0895 ,  G06F2212/1024 ,  G06F2212/1036 ,  G06F2212/401

    Abstract: A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.

    Abstract translation: 系统包括第一存储器和可耦合到第一存储器的装置。 该设备包括用于缓存来自第一存储器的数据的第二存储器。 第二存储器包括多行，每行包括对应的一组非均匀尺寸的压缩数据块和相应的一组标签块。 每个标签块表示该行的对应的压缩数据块。 该设备还包括解压缩逻辑以解压缩从第二存储器访问的数据块。 该设备还包括压缩逻辑以压缩要存储在第二存储器中的数据块。

    Creating SIMD efficient code by transferring register state through common memory
    25.
    发明授权
    Creating SIMD efficient code by transferring register state through common memory 有权
    通过公共存储器传送寄存器状态来创建SIMD高效代码

    公开(公告)号：US09354892B2

    公开(公告)日：2016-05-31

    申请号：US13689421

    申请日：2012-11-29

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Timothy G. Rogers ,  Bradford M. Beckmann ,  James M. O'Connor

    IPC: G06F9/00 ,  G06F7/36 ,  G06F9/38

    CPC classification number: G06F9/3887 ,  G06F9/3851

    Abstract: Methods, media, and computing systems are provided. The method includes, the media are configured for, and the computing system includes a processor with control logic for allocating memory for storing a plurality of local register states for work items to be executed in single instruction multiple data hardware and for repacking wavefronts that include work items associated with a program instruction responsive to a conditional statement. The repacking is configured to create repacked wavefronts that include at least one of a wavefront containing work items that all pass the conditional statement and a wavefront containing work items that all fail the conditional statement.

    Abstract translation: 提供了方法，媒体和计算系统。 该方法包括：媒体被配置用于计算系统，并且计算系统包括具有控制逻辑的处理器，该控制逻辑用于分配存储器，用于存储要在单指令多数据硬件中执行的工作项的多个本地寄存器状态，以及用于重新包装工作的波前 与响应于条件语句的程序指令相关联的项目。 重新配置被配置为创建重新包装的波前，其包括包含工作项的波前中的至少一个，所述工作项全部通过条件语句，以及包含所有未完成条件语句的工作项的波阵面。

    High level software execution mask override
    26.
    发明授权
    High level software execution mask override 有权
    高级软件执行掩码覆盖

    公开(公告)号：US09317296B2

    公开(公告)日：2016-04-19

    申请号：US13725063

    申请日：2012-12-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Timothy G. Rogers ,  Bradford M. Beckmann ,  James M. O'Connor

    IPC: G06F15/00 ,  G06F15/76 ,  G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3887 ,  G06F9/30036

    Abstract: Methods, and media, and computer systems are provided. The method includes, the media includes control logic for, and the computer system includes a processor with control logic for overriding an execution mask of SIMD hardware to enable at least one of a plurality of lanes of the SIMD hardware. Overriding the execution mask is responsive to a data parallel computation and a diverged control flow of a workgroup.

    Abstract translation: 提供了方法，媒体和计算机系统。 该方法包括：媒体包括用于的控制逻辑，并且计算机系统包括具有用于覆盖SIMD硬件的执行掩码的控制逻辑的处理器，以使能SIMD硬件的多个通道中的至少一个。 覆盖执行掩码响应于数据并行计算和工作组的分散控制流。

    HETEROGENEOUS FUNCTION UNIT DISPATCH IN A GRAPHICS PROCESSING UNIT
    28.
    发明申请
    HETEROGENEOUS FUNCTION UNIT DISPATCH IN A GRAPHICS PROCESSING UNIT 审中-公开
    图形处理单元中异构功能单元分配

    公开(公告)号：US20160085551A1

    公开(公告)日：2016-03-24

    申请号：US14490213

    申请日：2014-09-18

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Joseph L. Greathouse ,  Mitesh R. Meswani ,  Sooraj Puthoor ,  Dmitri Yudanov ,  James M. O'Connor

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/3887 ,  G06F9/3851

    Abstract: A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.

    Abstract translation: 呈现并行执行多个线程的计算单元。 计算单元包括一个或多个单指令多数据（SIMD）单元和读取和解码逻辑。 SIMD单元具有不同数量的算术逻辑单元（ALU），使得每个SIMD单元可以执行不同数量的线程。 获取和解码逻辑与每个SIMD单元通信，并且被配置为基于这样不同数量的ALU将线程分配给SIMD单元以供执行。

    DATA PROCESSOR AND METHOD OF LANE REALIGNMENT
    29.
    发明申请
    DATA PROCESSOR AND METHOD OF LANE REALIGNMENT 审中-公开
    数据处理器和LANE实现方法

    公开(公告)号：US20150100758A1

    公开(公告)日：2015-04-09

    申请号：US14045114

    申请日：2013-10-03

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Timothy G. Rogers ,  Bradford M. Beckmann ,  James M. O'Connor

    IPC: G06F9/38

    CPC classification number: G06F9/3887 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30123 ,  G06F9/3851

    Abstract: A data processor includes a register file divided into at least a first portion and a second portion for storing data. A single instruction, multiple data (SIMD) unit is also divided into at least a first lane and a second lane. The first and second lanes of the SIMD unit correspond respectively to the first and second portions of the register file. Furthermore, each lane of the SIMD unit is capable of data processing. The data processor also includes a realignment element in communication with the register file and the SIMD unit. The realignment element is configured to selectively realign conveyance of data between the first portion of the register file and the first lane of the SIMD unit to the second lane of the SIMD unit.

    Abstract translation: 数据处理器包括被分成至少第一部分的寄存器文件和用于存储数据的第二部分。 单指令，多数据（SIMD）单元也被划分为至少第一通道和第二通道。 SIMD单元的第一和第二通道分别对应于寄存器文件的第一和第二部分。 此外，SIMD单元的每个通道能够进行数据处理。 数据处理器还包括与寄存器文件和SIMD单元通信的重新对准元件。 重新对准元件被配置为选择性地将寄存器文件的第一部分与SIMD单元的第一通道之间的数据传送到SIMD单元的第二通道。

    Compound Memory Operations in a Logic Layer of a Stacked Memory
    30.
    发明申请
    Compound Memory Operations in a Logic Layer of a Stacked Memory 审中-公开
    堆叠存储器的逻辑层中的复合存储器操作

    公开(公告)号：US20140181427A1

    公开(公告)日：2014-06-26

    申请号：US13724338

    申请日：2012-12-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Nuwan S. JAYASENA ,  James M. O'Connor ,  Gabriel H. Loh ,  Michael J. Schulte ,  Bradford M. Beckmann ,  Michael Ignatowski

    IPC: G06F12/00

    CPC classification number: G06F9/3004 ,  G06F9/3455 ,  G06F15/7821

    Abstract: Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various data movement and address calculation operations. This functionality would allow compound memory operations—a single request communicated to the memory that characterizes the accesses and movement of many data items. This eliminates the performance and power overheads associated with communicating address and control information on a fine-grain, per-data-item basis from a host processor (or other device) to the memory. This approach also provides better visibility of macro-level memory access patterns to the memory system and may enable additional optimizations in scheduling memory accesses.

    Abstract translation: 除了一层或多层DRAM（或其他存储器技术）之外，一些堆叠堆叠的存储器将包含逻辑层。 该逻辑层可以是与存储器管芯堆叠相关联的硅插入器上的离散逻辑管芯或逻辑。 额外的电路/功能被放置在逻辑层上以实现执行各种数据移动和地址计算操作的功能。 该功能将允许复合存储器操作 - 传达到存储器的单个请求，其表征许多数据项的访问和移动。 这消除了与从主处理器（或其他设备）到存储器的以细粒度，每数据项为基础传送地址和控制信息相关联的性能和功耗开销。 这种方法还提供了对存储器系统的宏级存储器访问模式的更好的可见性，并且可以在调度存储器访问中实现附加优化。

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