公开(公告)号：US08869009B2

公开(公告)日：2014-10-21

申请号：US13764083

申请日：2013-02-11

Applicant: Apple Inc.

Inventor： Eyal Gurgi ,  Tomer Ish-Shalom

IPC: G11C29/00 ,  H03M13/00 ,  G06F11/10 ,  H03M13/35

CPC classification number: G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  H03M13/35

Abstract: A method includes, in a memory controller that controls a memory, receiving from a host a read command that specifies data to be retrieved from the memory and further specifies a target error performance to be achieved in retrieving the data. A data retrieval configuration is selected in the memory controller depending on the target error performance specified in the read command. The data is retrieved from the memory using the selected data retrieval configuration, and the retrieved data is output to the host.

Abstract translation: 一种方法包括：在控制存储器的存储器控​​制器中，从主机接收指定要从存储器检索的数据的读取命令，并进一步指定在检索数据时要实现的目标错误性能。 根据读取命令中指定的目标错误性能，在存储器控制器中选择数据检索配置。 使用所选择的数据检索配置从存储器检索数据，并将检索到的数据输出到主机。

公开(公告)号：US20140229794A1

公开(公告)日：2014-08-14

申请号：US13764083

申请日：2013-02-11

Applicant: APPLE INC.

Inventor： Eyal Gurgi ,  Tomer Ish-Shalom

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  H03M13/35

Abstract: A method includes, in a memory controller that controls a memory, receiving from a host a read command that specifies data to be retrieved from the memory and further specifies a target error performance to be achieved in retrieving the data. A data retrieval configuration is selected in the memory controller depending on the target error performance specified in the read command. The data is retrieved from the memory using the selected data retrieval configuration, and the retrieved data is output to the host.

公开(公告)号：US20140229699A1

公开(公告)日：2014-08-14

申请号：US13763928

申请日：2013-02-11

Applicant: APPLE INC.

Inventor： Eyal Gurgi ,  Tomer Ish-Shalom

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F13/1626 ,  G11C16/06

Abstract: An apparatus includes a memory and storage circuitry. The storage circuitry is configured to receive at least one request causing execution of a sequence of memory commands in the memory, to identify that, although a first memory command appears in the sequence before a second memory command, the execution of the second memory command would improve a performance of the execution of the first memory command, and to execute the second memory command and then to execute the first memory command with the improved execution performance.

Abstract translation: 一种装置包括存储器和存储电路。 存储电路被配置为接收至少一个请求，从而在存储器中执行一系列存储器命令，以便识别尽管在第二存储器命令之前的序列中出现第一存储器命令，但是第二存储器命令的执行将 提高执行第一存储器命令的性能，并且执行第二存储器命令，然后执行具有改进的执行性能的第一存储器命令。

公开(公告)号：US10438683B2

公开(公告)日：2019-10-08

申请号：US15810166

申请日：2017-11-13

Applicant: Apple Inc.

Inventor： Barak Sagiv ,  Einav Yogev ,  Eli Yazovitsky ,  Eyal Gurgi ,  Roi Solomon

IPC: G11C29/44 ,  G11C29/38 ,  G11C29/02

Abstract: A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.

公开(公告)号：US10146460B1

公开(公告)日：2018-12-04

申请号：US15716703

申请日：2017-09-27

Applicant: Apple Inc.

Inventor： Barak Baum ,  Barak Sagiv ,  Einav Yogev ,  Eyal Gurgi ,  Ariel Landau

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F11/002 ,  G06F11/1048 ,  G06F11/1072 ,  G06F11/108 ,  G06F11/3058 ,  G11C7/04 ,  G11C11/5642

Abstract: A memory system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells that store data by setting the memory cells to analog voltages representative of respective storage values. The storage circuitry is configured to receive data for storage, to measure a temperature at a time of programming the received data, and, to program the received data to the memory cells using a first programming scheme when the measured temperature falls within a predefined normal temperature range, and otherwise to program the received data to the memory cells using a second programming scheme having a lower net storage utilization than the first programming scheme.

公开(公告)号：US09672925B2

公开(公告)日：2017-06-06

申请号：US15066020

申请日：2016-03-10

Applicant: Apple Inc.

Inventor： Arik Rizel ,  Avraham Poza Meir ,  Yael Shur ,  Eyal Gurgi ,  Barak Baum

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  H01L29/423 ,  H01L27/11568

CPC classification number: G11C16/24 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11568 ,  H01L29/42328

Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.

公开(公告)号：US09502120B2

公开(公告)日：2016-11-22

申请号：US14318876

申请日：2014-06-30

Applicant: Apple Inc.

Inventor： Yoav Kasorla ,  Naftali Sommer ,  Eyal Gurgi ,  Micha Anholt

IPC: G11C16/10 ,  G11C27/00 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/12

CPC classification number: G11C27/005 ,  G06F11/1048 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5647 ,  G11C2211/5648

Abstract: A method for data storage includes accepting data for storage in an array of memory cells, which are arranged in rows associated with respective word lines. Data is stored in one or more memory cells of the array using one or more programming levels. In response to a determination that a first memory cell of the one or more memory cells is subject to distortion, a second memory cell may be programmed to a predetermined programming level.

Abstract translation: 一种用于数据存储的方法包括接收用于存储在与各个字线相关联的行中的存储器单元阵列中的数据。 使用一个或多个编程级别将数据存储在阵列的一个或多个存储单元中。 响应于确定一个或多个存储器单元的第一存储器单元经历失真，第二存储器单元可被编程为预定的编程级别。

公开(公告)号：US20160336078A1

公开(公告)日：2016-11-17

申请号：US15221947

申请日：2016-07-28

Applicant: Apple Inc.

Inventor： Eyal Gurgi ,  Yoav Kasorla ,  Barak Rotbard ,  Shai Ojalvo

IPC: G11C29/38 ,  G11C16/34 ,  G11C29/44 ,  G11C29/50 ,  G11C16/10 ,  G11C29/12

CPC classification number: G11C29/38 ,  G06F11/07 ,  G06F11/073 ,  G06F11/0772 ,  G06F11/263 ,  G11C11/1677 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5678 ,  G11C13/0035 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/12015 ,  G11C29/44 ,  G11C29/50012

Abstract: A method for data storage includes receiving in a memory device data for storage in a group of memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.

公开(公告)号：US09390809B1

公开(公告)日：2016-07-12

申请号：US14617961

申请日：2015-02-10

Applicant: APPLE INC.

Inventor： Yael Shur ,  Avraham Poza Meir ,  Barak Baum ,  Eyal Gurgi

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C29/00

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/70 ,  G11C2029/1202

Abstract: A method includes defining a normal voltage configuration for application to word lines (WLs) and Bit lines (BLs) of a memory block, and a an abnormal voltage configuration, different from the normal voltage configuration, for application to the WLs and the BLs of the memory block when a word-line-to-word-line (WL-WL) short-circuit is found between at least two of the WLs in the memory block. If no WL-WL short-circuit is found in the memory block, a data storage operation is performed in the memory block by applying the normal voltage configuration. If a WL-WL short-circuit is found in the memory block, the data storage operation is performed in the memory block by applying the abnormal voltage configuration.

Abstract translation: 一种方法包括定义用于应用于存储块的字线（WL）和位线（BL）的正常电压配置以及不同于正常电压配置的异常电压配置，以应用于WL和BL 当在存储器块中的至少两个WL之间找到字线到字线（WL-WL）短路时，存储块。 如果在存储块中没有发现WL-WL短路，则通过施加正常电压配置在存储块中执行数据存储操作。 如果在存储器块中发现WL-WL短路，则通过应用异常电压配置在存储块中执行数据存储操作。

公开(公告)号：US20160093386A1

公开(公告)日：2016-03-31

申请号：US14962333

申请日：2015-12-08

Applicant: Apple Inc.

Inventor： Yael Shur ,  Yoav Kasorla ,  Moshe Neerman ,  Naftali Sommer ,  Avraham Poza Meir ,  Etai Zaltsman ,  Eyal Gurgi ,  Meir Dalal

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/349

Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

Abstract translation: 一种非易失性存储器中的方法，其包括使用包括擦除级别的预定义编程级别集存储数据的多个存储器单元，包括接收指示要保留的一组存储器单元的存储操作，而不进行编程 长时间 组中的存储单元被设置为与擦除的电平不同的保持编程电平。 在准备使用数据对存储器单元组进行编程时，存储器单元组被擦除到擦除的电平，然后将数据编程在存储器单元组中。