公开(公告)号：US07177970B2

公开(公告)日：2007-02-13

申请号：US10274881

申请日：2002-10-22

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F13/14 ,  G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

摘要翻译： 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US06341323B2

公开(公告)日：2002-01-22

申请号：US09777960

申请日：2001-02-07

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F1300

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

摘要翻译： 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US6005599A

公开(公告)日：1999-12-21

申请号：US363331

申请日：1994-12-23

申请人： Mitsuo Asai ,  Yoshihiro Takiyasu ,  Koichi Shibata ,  Mikiko Sato ,  Atsushi Saito ,  Takehisa Hayashi ,  Masaru Igawa

发明人： Mitsuo Asai ,  Yoshihiro Takiyasu ,  Koichi Shibata ,  Mikiko Sato ,  Atsushi Saito ,  Takehisa Hayashi ,  Masaru Igawa

IPC分类号： G06F13/00 ,  H04N5/765 ,  H04N5/781 ,  H04N5/783 ,  H04N5/85 ,  H04N5/926 ,  H04N5/93 ,  H04N7/10 ,  H04N7/173 ,  H04N21/231 ,  H04N21/2387

CPC分类号： H04N7/10 ,  H04N5/926 ,  H04N5/765 ,  H04N5/781 ,  H04N5/783 ,  H04N5/85

摘要： In a video storage and delivery apparatus and corresponding system, video data items are simultaneously supplied to a plurality of users while guaranteeing the time axis and the picture quality of the video data. The apparatus includes a frame address table which indicates a storage location in the apparatus of each frame of video data to start a special reproduction or a reproduction at a desired frame and a control unit controlling a switch bus connecting a plurality of video storage and delivery apparatuses to a plurality of channels so as to conduct data transfers via the switch bus between the apparatuses and between video reproduction devices of the users. From an optical disk data storage storing video data, a plurality of video data items are read in a timesharing fashion to be temporarily stored in a magnetic disk device or a semiconductor memory, thereby delivering the video data items therefrom to the users.

摘要翻译： 在视频存储和传送装置和相应的系统中，视频数据项同时提供给多个用户，同时保证视频数据的时间轴和图像质量。 该装置包括帧地址表，其指示在每个视频数据帧的装置中的存储位置，以开始特定再现或在期望帧的再现;以及控制单元，控制连接多个视频存储和传送装置的开关总线 到多个信道，以便经由设备之间的交换总线和用户的视频再现设备之间进行数据传送。 从存储视频数据的光盘数据存储器中，以分时方式读取多个视频数据项，临时存储在磁盘装置或半导体存储器中，由此向用户传送视频数据。

公开(公告)号：US5339396A

公开(公告)日：1994-08-16

申请号：US119601

申请日：1993-09-10

申请人： Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Takehisa Hayashi ,  Teruo Tanaka ,  Shigeo Nagashima

发明人： Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Takehisa Hayashi ,  Teruo Tanaka ,  Shigeo Nagashima

IPC分类号： G06F13/40 ,  G06F15/173 ,  G06F13/00

CPC分类号： G06F15/17375 ,  G06F13/4022 ,  G06F15/17381

摘要： In a parallel computer including L=n.sub.1 x n.sub.2 x - - - x n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L x (1/n.sub.1 +1/n.sub.2 +- - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N) , 0.ltoreq.i.sub.1 .ltoreq.n.sub.1-1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2-1, - - - , 0.ltoreq.i.sub.n .ltoreq.n.sub.N-1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coordinates(i.sub.1, i.sub.2, - - - , n.sub.k-1, n.sub.k+1, - - - , i.sub.N)of N-1 dimensional subspace excluding the k-th dimension, the interconnection being further performed for all values of k (1.ltoreq.k.ltoreq.N).

摘要翻译： 在包括L = n 1 x n 2 x - - - x n N个处理器元件或者外部设备（以下由处理器元件表示）的并行计算机中，使用L x（1 / n1 + 1 / n2 + - - + 1 / nN）交叉开关总共包括N维网格坐标（i1，i2，...，iN），0 （ i1，i2，...，1，...，iN）。 。 。 （i1，i2，...，nk-1，...，iN）通过使用一个交叉开关，每个交叉开关具有nk个输入和nk个输出，并且相对于所有（L / nk组）除了第k维之外的N-1维子空间的坐标（i1，i2， - - ，nk-1，nk + 1， - - ，iN），对于 k（1

公开(公告)号：US5307266A

公开(公告)日：1994-04-26

申请号：US741760

申请日：1991-08-07

申请人： Takehisa Hayashi ,  Kouki Noguchi ,  Tsuneya Kurihara ,  Masahiro Abe

发明人： Takehisa Hayashi ,  Kouki Noguchi ,  Tsuneya Kurihara ,  Masahiro Abe

IPC分类号： G06F17/30 ,  G06F15/40

CPC分类号： G06F17/30011

摘要： A document processing system for processing documents by using structured keywords comprises an output system and a receiver system. The output system includes a first storage for storing a structured keyword dictionary containing structured keywords among which relations are systematically structured, and linkage unit providing linkage information for establishing correspondences between constituent parts of an input document and corresponding ones of the keywords. The receiver system is coupled to the output system and includes a second storage for storing structured keywords among which relations are systematically structured, and retrieving unit having inputs supplied with the document and the linkage information for retrieving the document to thereby form data of a predetermined edition format by using the structured keyword read out from the second storage. Data transfer between the output system and the receiver systems can be performed either on-line or off-line.

摘要翻译： 通过使用结构化关键词处理文档的文档处理系统包括输出系统和接收器系统。 输出系统包括：第一存储器，用于存储包含结构化关键字的结构化关键字字典，其中系统地构造关系;以及链接单元，提供用于建立输入文档的组成部分与对应关键字之间的对应关系的链接信息。 接收机系统耦合到输出系统，并且包括用于存储结构化关键字的第二存储器，其中系统地构造关系，以及具有提供有文档的输入的检索单元和用于检索文档的链接信息，从而形成预定版本的数据 通过使用从第二个存储器读出的结构化关键字的格式。 输出系统和接收机系统之间的数据传输可以在线还是离线进行。

公开(公告)号：US5253197A

公开(公告)日：1993-10-12

申请号：US580464

申请日：1990-09-11

申请人： Makoto Suzuki ,  Suguru Tachibana ,  Hisayuki Higuchi ,  Katsuhiro Shimohigashi ,  Takehisa Hayashi ,  Makoto Hanawa ,  Tadahiko Nishimukai

发明人： Makoto Suzuki ,  Suguru Tachibana ,  Hisayuki Higuchi ,  Katsuhiro Shimohigashi ,  Takehisa Hayashi ,  Makoto Hanawa ,  Tadahiko Nishimukai

IPC分类号： G06F12/08 ,  G06F12/10 ,  G11C15/04

CPC分类号： G11C15/04 ,  G06F12/0895 ,  G06F12/1054 ,  Y02B60/1225

摘要： In a first embodiment of a CAM (Content Addressable Memory) or cache memory of the present invention disclosed herein, comparing information stored in a memory cell with comparison input information is accomplished in a comparison circuit without first converting a readout current from the memory cell into voltage information. In another embodiment, a matching detection between first stored information outputted from a first memory cell array and second stored information outputted from a second memory cell array is accomplished by an integrally formed sensing and matching detection circuit which is characterized as having both sensing and matching detection capabilities. That is, the sensing and matching detection circuit senses both stored information and thereafter detects matching based on a sensing result.

摘要翻译： 在本文公开的本发明的CAM（内容可寻址存储器）或高速缓冲存储器的第一实施例中，将存储在存储单元中的比较信息与比较输入信息进行比较，在比较电路中完成，而无需将来自存储单元的读出电流转换成 电压信息。 在另一个实施例中，从第一存储单元阵列输出的第一存储信息与从第二存储单元阵列输出的第二存储信息之间的匹配检测由一体形成的感测和匹配检测电路来实现，其特征在于具有检测和匹配检测 能力 也就是说，感测和匹配检测电路感测存储的信息，并且此后基于感测结果检测匹配。

公开(公告)号：US20070106832A1

公开(公告)日：2007-05-10

申请号：US11642511

申请日：2006-12-21

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

公开(公告)号：US5935205A

公开(公告)日：1999-08-10

申请号：US670757

申请日：1996-06-21

申请人： Hideki Murayama ,  Hiroshi Yashiro ,  Satoshi Yoshizawa ,  Kazuo Horikawa ,  Takehisa Hayashi ,  Hiroshi Iwamoto ,  Kimitoshi Yamada

发明人： Hideki Murayama ,  Hiroshi Yashiro ,  Satoshi Yoshizawa ,  Kazuo Horikawa ,  Takehisa Hayashi ,  Hiroshi Iwamoto ,  Kimitoshi Yamada

IPC分类号： G06F13/14 ,  G06F1/00 ,  G06F3/06 ,  G06F12/14 ,  G06F13/00 ,  G06F15/17 ,  G06F21/00 ,  G06F21/24 ,  G06F13/38

CPC分类号： G06F3/062 ,  G06F21/80 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/067

摘要： A computer system having a plurality of computers connected to each other by a computer coupling mechanism. Each computer includes a processor, memory, I/O device, disk control mechanism, computer coupling network adapter, disk requirement processing section connected to a system bus, and a disk connected to a disk control mechanism. The disk requirement processing section controls the disk, in response to a processing requirement for the disk from one of the processors of the other computers, based on structural definition information. The structural definition information describes a structure of the computer system. The computer system may be a loosely-coupled computer system.

摘要翻译： 一种具有通过计算机连接机构彼此连接的多个计算机的计算机系统。 每个计算机包括处理器，存储器，I / O设备，磁盘控制机构，计算机耦合网络适配器，连接到系统总线的磁盘需求处理部分以及连接到磁盘控制机构的磁盘。 磁盘需求处理部分基于结构定义信息响应于来自其他计算机的其中一个处理器的磁盘的处理要求来控制磁盘。 结构定义信息描述了计算机系统的结构。 计算机系统可以是松散耦合的计算机系统。

公开(公告)号：US5870594A

公开(公告)日：1999-02-09

申请号：US963857

申请日：1997-11-04

申请人： Toshio Doi ,  Takehisa Hayashi ,  Tetsuo Nakano

发明人： Toshio Doi ,  Takehisa Hayashi ,  Tetsuo Nakano

IPC分类号： G06F13/42 ,  G06F1/12 ,  H04J3/06 ,  H04L7/02 ,  G06F1/06

CPC分类号： H04L7/02

摘要： The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

摘要翻译： 通过根据通过检测采样偏差确定的误差信号的反馈来控制接收机采样时钟和主时钟之间的相位差，相对于用于发起发送的主时钟，连续地调整接收机处的数字信号采样定时 在启动操作和正常操作期间，从期望的基准定时的时钟定时。 通过将采样时钟设置在启动时的所需参考时序来补偿各个器件中的传播延迟散射。 通过在正常工作期间根据接收到的数字信号检测采样时钟定时与参考定时的偏差，然后根据检测结果连续校正采样时钟定时来补偿在器件工作期间引起的传播延迟散射。

公开(公告)号：US5835492A

公开(公告)日：1998-11-10

申请号：US529762

申请日：1995-09-18

申请人： Takeshi Aimoto ,  Hidenori Inouchi ,  Shoichi Murase ,  Shinichi Tanabe ,  Kazuhiro Hashimoto ,  Hiroshi Iwamoto ,  Hiroshi Ohguro ,  Takehisa Hayashi ,  Haruyuki Nakayama ,  Kenji Nakajima ,  Satoshi Yoshizawa ,  Hideki Murayama

发明人： Takeshi Aimoto ,  Hidenori Inouchi ,  Shoichi Murase ,  Shinichi Tanabe ,  Kazuhiro Hashimoto ,  Hiroshi Iwamoto ,  Hiroshi Ohguro ,  Takehisa Hayashi ,  Haruyuki Nakayama ,  Kenji Nakajima ,  Satoshi Yoshizawa ,  Hideki Murayama

IPC分类号： H04L12/56 ,  H04L29/06 ,  H04L29/08 ,  H04L29/14 ,  H04J3/24

CPC分类号： H04L49/505 ,  H04L12/56 ,  H04L29/06 ,  H04L47/10 ,  H04L47/32 ,  H04L49/253 ,  H04L69/40 ,  H04L49/30 ,  H04L49/555 ,  H04L69/22 ,  H04L69/329

摘要： A data communication system for a computer system in which computers are mutually connected includes: each computer having an area to store a command to execute data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the computers; and a transmission permitting component, connected between the switch circuit and one of the computers, for outputting a signal to permit the data transmission from one computer to another computer; a communication component for transmitting the data received from one computer by outputting the transmission permission signal from the transmission permitting component to another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from one computer to another computer; and a communication control component to abandon the data that is subsequently received from one computer by outputting the transmission permission signal in accordance with an output of the detecting component. When the abnormality occurs, the switch circuit releases another computer, thereby disconnecting one computer and another computer. When reception commands prepared in the buffer area of another computer are perfectly used, another computer abandons the packet which does not include the flag to instruct the continuous reception.

摘要翻译： 一种用于计算机相互连接的计算机系统的数据通信系统包括：每个计算机具有存储用于根据其执行数据通信的命令的区域和用于存储数据的缓冲区; 用于相互选择性地连接计算机的开关电路; 以及连接在开关电路和其中一台计算机之间的传输允许部件，用于输出信号以允许从一台计算机到另一台计算机的数据传输; 通信部件，用于通过将所述传输许可部件通过所述开关电路输出到另一计算机的传输许可信号，发送从一台计算机接收的数据; 检测部件，用于检测从一个计算机到另一个计算机的关于数据通信的异常的发生; 以及通信控制部件，通过根据检测部件的输出输出发送允许信号，放弃随后从一台计算机接收到的数据。 当异常发生时，开关电路释放另一台计算机，从而断开一台计算机和另一台计算机的连接。 当在另一计算机的缓冲区中准备的接收命令被完美地使用时，另一台计算机放弃不包括该标志的分组来指示连续接收。