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公开(公告)号:US20140089707A1
公开(公告)日:2014-03-27
申请号:US13788366
申请日:2013-03-07
Applicant: Atmel Corporation
Inventor: Sebastien Jouin , Romain Oddoart , Patrice Menard , Mickael Le Dily , Thierry Gourbilleau
IPC: G06F1/32
CPC classification number: G06F1/3243 , G06F1/3296 , Y02D10/152 , Y02D10/172
Abstract: A microcontroller system can operate in a number of power modes. In response to changing from a previous mode to a present mode, the microcontroller system reads a present calibration value correspond to the present mode from system configuration storage and write the present calibration value to a configuration register for a component. A logic block for the component reads the present calibration value and calibrates the component.
Abstract translation: 微控制器系统可以在多种功率模式下工作。 响应于从先前模式变为当前模式,微控制器系统从系统配置存储读取对应于当前模式的当前校准值,并将当前校准值写入组件的配置寄存器。 组件的逻辑块读取当前校准值并校准组件。
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公开(公告)号:US10296077B2
公开(公告)日:2019-05-21
申请号:US15171695
申请日:2016-06-02
Applicant: Atmel Corporation
Inventor: Sebastien Jouin , Patrice Menard , Thierry Gourbilleau
IPC: G06F1/32 , G06F1/3296 , G06F1/3234 , G06F1/3228 , G06F1/3215 , G06F1/3203
Abstract: A microcontroller system is organized into power domains. A power manager of the microcontroller system can change the power configuration of a power domain based on whether the microcontroller system has asserted a power trigger for any module in the power domain or if any module in the power domain has asserted a power keeper.
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公开(公告)号:US09811111B2
公开(公告)日:2017-11-07
申请号:US15172661
申请日:2016-06-03
Applicant: Atmel Corporation
Inventor: Sebastien Jouin , Patrice Menard , Thierry Gourbilleau , Yann Le Floch , Mohamed Aichouchi
CPC classification number: G06F1/06 , G06F1/10 , G06F1/3237 , G06F2217/62 , H03K19/0016 , Y02D10/128
Abstract: A clock generation system for an integrated circuit (IC) chip (e.g., a microcontroller) is disclosed that allows digital blocks and other components in the IC chip to start and stop internal clocks dynamically on demand to reduce power consumption.
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公开(公告)号:US20170132051A1
公开(公告)日:2017-05-11
申请号:US15412198
申请日:2017-01-23
Applicant: Atmel Corporation
Inventor: Frode Milch Pedersen , Sebastien Jouin , Stein Danielsen , Francois Fosse , Thierry Delalande , Ivar Holand , James Halliman
CPC classification number: G06F9/526 , G06F11/00 , G06F11/004 , G06F13/122 , G06F13/28 , G06F13/362 , G06F13/4004 , G06F13/4282 , G06F17/30362 , G06F2201/825
Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.
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公开(公告)号:US20160274654A1
公开(公告)日:2016-09-22
申请号:US15082056
申请日:2016-03-28
Applicant: Atmel Corporation
Inventor: Sebastien Jouin , Romain Oddoart , Patrice Menard , Mickael Le Dily , Thierry Gourbilleau
CPC classification number: G06F1/3296 , G06F1/266 , G06F9/4418 , G06F13/24 , Y02D10/172 , Y02D50/20
Abstract: A voltage scaling system can scale a supply voltage while preventing processor access of system components that are rendered unstable from the scaling. A processor receives an instruction to scale a system supply voltage to a target supply voltage. The processor executes the instruction and enters into a sleep mode. The processor can send, to a controller that saves power, an indication that the processor is in the sleep mode. When the processor is in the sleep mode, the processor becomes inactive and cannot access any components, e.g., Flash memory data, of the voltage scaling system. The controller can configure a voltage regulator to scale the system supply voltage to the target supply voltage. Once the target supply voltage is reached, the voltage regulator sends an interrupt to the processor, thereby waking up the processor from the sleep mode.
Abstract translation: 电压调节系统可以缩放电源电压,同时防止处理器访问因缩放而变得不稳定的系统组件。 处理器接收将系统电源电压缩放到目标电源电压的指令。 处理器执行指令并进入睡眠模式。 处理器可以向节省电力的控制器发送处理器处于睡眠模式的指示。 当处理器处于睡眠模式时,处理器变为不活动状态,并且不能访问电压缩放系统的任何组件,例如闪存数据。 控制器可以配置电压调节器,以将系统电源电压缩放到目标电源电压。 一旦达到目标电源电压,电压调节器向处理器发送中断,从而将处理器从睡眠模式唤醒。
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公开(公告)号:US09383805B2
公开(公告)日:2016-07-05
申请号:US13797538
申请日:2013-03-12
Applicant: Atmel Corporation
Inventor: Sebastien Jouin , Patrice Menard , Thierry Gourbilleau , Yann Le Floch , Mohamed Aichouchi
CPC classification number: G06F1/06 , G06F1/10 , G06F1/3237 , G06F2217/62 , H03K19/0016 , Y02D10/128
Abstract: A clock generation system for an integrated circuit (IC) chip (e.g., a microcontroller) is disclosed that allows digital blocks and other components in the IC chip to start and stop internal clocks dynamically on demand to reduce power consumption.
Abstract translation: 公开了用于集成电路(IC)芯片(例如,微控制器)的时钟发生系统,其允许IC芯片中的数字模块和其他组件根据需要动态地启动和停止内部时钟以降低功耗。
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公开(公告)号:US20140281156A1
公开(公告)日:2014-09-18
申请号:US13941671
申请日:2013-07-15
Applicant: ATMEL CORPORATION
Inventor: Frode Milch Pedersen , Sebastien Jouin , Ian Fullerton
IPC: G06F12/02
CPC classification number: G06F3/0611 , G06F3/0655 , G06F3/0679 , G06F13/1689 , G06F13/4217 , G06F13/4243 , Y02D10/14 , Y02D10/151
Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.
Abstract translation: 从非易失性存储器件接收指示非易失性存储器件的当前访问时间的锁存信号。 访问时间表示非易失性存储器件根据数据请求使数据可用的时间量。 接收总线系统时钟信号。 评估锁存信号,并且基于评估来调整非易失性存储器件的等待状态。 等待状态表示由中央处理单元用于访问非易失性存储器件的总线系统时钟的周期数。 产生基于调整后的等待状态触发的总线系统数据就绪信号。 当触发时,总线系统数据就绪信号表示响应于该请求可用数据。
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