CHANGING POWER MODES OF A MICROCONTROLLER SYSTEM
    21.
    发明申请
    CHANGING POWER MODES OF A MICROCONTROLLER SYSTEM 有权
    改变微控制器系统的电源模式

    公开(公告)号:US20140089707A1

    公开(公告)日:2014-03-27

    申请号:US13788366

    申请日:2013-03-07

    CPC classification number: G06F1/3243 G06F1/3296 Y02D10/152 Y02D10/172

    Abstract: A microcontroller system can operate in a number of power modes. In response to changing from a previous mode to a present mode, the microcontroller system reads a present calibration value correspond to the present mode from system configuration storage and write the present calibration value to a configuration register for a component. A logic block for the component reads the present calibration value and calibrates the component.

    Abstract translation: 微控制器系统可以在多种功率模式下工作。 响应于从先前模式变为当前模式,微控制器系统从系统配置存储读取对应于当前模式的当前校准值,并将当前校准值写入组件的配置寄存器。 组件的逻辑块读取当前校准值并校准组件。

    VOLTAGE SCALING SYSTEM WITH SLEEP MODE
    25.
    发明申请
    VOLTAGE SCALING SYSTEM WITH SLEEP MODE 审中-公开
    具有休眠模式的电压调节系统

    公开(公告)号:US20160274654A1

    公开(公告)日:2016-09-22

    申请号:US15082056

    申请日:2016-03-28

    Abstract: A voltage scaling system can scale a supply voltage while preventing processor access of system components that are rendered unstable from the scaling. A processor receives an instruction to scale a system supply voltage to a target supply voltage. The processor executes the instruction and enters into a sleep mode. The processor can send, to a controller that saves power, an indication that the processor is in the sleep mode. When the processor is in the sleep mode, the processor becomes inactive and cannot access any components, e.g., Flash memory data, of the voltage scaling system. The controller can configure a voltage regulator to scale the system supply voltage to the target supply voltage. Once the target supply voltage is reached, the voltage regulator sends an interrupt to the processor, thereby waking up the processor from the sleep mode.

    Abstract translation: 电压调节系统可以缩放电源电压,同时防止处理器访问因缩放而变得不稳定的系统组件。 处理器接收将系统电源电压缩放到目标电源电压的指令。 处理器执行指令并进入睡眠模式。 处理器可以向节省电力的控制器发送处理器处于睡眠模式的指示。 当处理器处于睡眠模式时,处理器变为不活动状态,并且不能访问电压缩放系统的任何组件,例如闪存数据。 控制器可以配置电压调节器,以将系统电源电压缩放到目标电源电压。 一旦达到目标电源电压,电压调节器向处理器发送中断,从而将处理器从睡眠模式唤醒。

    MANAGING WAIT STATES FOR MEMORY ACCESS
    27.
    发明申请
    MANAGING WAIT STATES FOR MEMORY ACCESS 有权
    管理用于存储器访问的等待状态

    公开(公告)号:US20140281156A1

    公开(公告)日:2014-09-18

    申请号:US13941671

    申请日:2013-07-15

    Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

    Abstract translation: 从非易失性存储器件接收指示非易失性存储器件的当前访问时间的锁存信号。 访问时间表示非易失性存储器件根据数据请求使数据可用的时间量。 接收总线系统时钟信号。 评估锁存信号,并且基于评估来调整非易失性存储器件的等待状态。 等待状态表示由中央处理单元用于访问非易失性存储器件的总线系统时钟的周期数。 产生基于调整后的等待状态触发的总线系统数据就绪信号。 当触发时,总线系统数据就绪信号表示响应于该请求可用数据。

Patent Agency Ranking