公开(公告)号：US20130111121A1

公开(公告)日：2013-05-02

申请号：US13285465

申请日：2011-10-31

申请人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Wiessman ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

发明人： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Wiessman ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

摘要： In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明涉及具有多个核心的处理器和耦合到核心并且包括多个分区的高速缓冲存储器。 处理器还可以包括基于在至少一个核上执行的工作负载的存储器有界性来动态地改变高速缓存存储器的大小的逻辑。 描述和要求保护其他实施例。

公开(公告)号：US20120254641A1

公开(公告)日：2012-10-04

申请号：US13077618

申请日：2011-03-31

申请人： Efraim Rotem ,  Avinash N. Ananthakrishnan ,  Doron Rajwan ,  Kosta Luria ,  Ronny Korner

发明人： Efraim Rotem ,  Avinash N. Ananthakrishnan ,  Doron Rajwan ,  Kosta Luria ,  Ronny Korner

IPC分类号： G06F1/32

CPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/3243 ,  G06F11/004 ,  G06F11/3024 ,  G06F11/3058 ,  G06F11/348 ,  G06F2201/81 ,  G06F2201/86 ,  Y02D10/152

摘要： An apparatus may comprise one or more processor cores of a processor and a set of current limiters. Each current limiter may be coupled to a respective processor core and arranged to monitor processor activity in the processor, to compare the processor activity to one or more current limits of multiple current limits; and to initiate a current-limiting action when the one or more current limits is exceeded.

摘要翻译： 设备可以包括处理器的一个或多个处理器核心和一组限流器。 每个限流器可以耦合到相应的处理器核心并且被布置成监视处理器中的处理器活动，以将处理器活动与多个电流限制的一个或多个电流限制进行比较; 并且当超过一个或多个电流限制时启动限流动作。

公开(公告)号：US20130080804A1

公开(公告)日：2013-03-28

申请号：US13247580

申请日：2011-09-28

申请人： Avinash N. Ananthakrishan ,  Tomer Ziv ,  Doron Rajwan ,  Efraim Rotem

发明人： Avinash N. Ananthakrishan ,  Tomer Ziv ,  Doron Rajwan ,  Efraim Rotem

IPC分类号： G06F1/32

CPC分类号： G06F1/3234 ,  G06F1/206 ,  G06F1/324 ,  Y02D10/16

摘要： In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.

公开(公告)号：US08954770B2

公开(公告)日：2015-02-10

申请号：US13247580

申请日：2011-09-28

申请人： Avinash N. Ananthakrishan ,  Tomer Ziv ,  Doron Rajwan ,  Efraim Rotem

发明人： Avinash N. Ananthakrishan ,  Tomer Ziv ,  Doron Rajwan ,  Efraim Rotem

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F1/20

CPC分类号： G06F1/3234 ,  G06F1/206 ,  G06F1/324 ,  Y02D10/16

摘要： In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于在多域处理器的控制器中确定多域处理器的第二域的温度是否大于节流阀阈值和跨域之和的方法 余量，如果是，则将多域处理器的第一域的频率降低所选择的量。 以这种方式，由于域的热耦合，可以允许第二域的温度降低。 描述和要求保护其他实施例。

公开(公告)号：US08707060B2

公开(公告)日：2014-04-22

申请号：US12263431

申请日：2008-10-31

申请人： Efraim Rotem ,  Doron Rajwan ,  Lev Finkelstein

发明人： Efraim Rotem ,  Doron Rajwan ,  Lev Finkelstein

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/206 ,  Y02D10/16

摘要： Methods and apparatus relating to deterministic management of dynamic thermal response of processors are described. In one embodiment, available thermal headroom may be used to extract the performance potential in a deterministic way, e.g., such that it reduces or even eliminates the product-to-product variations. Other embodiments are also disclosed and claimed.

摘要翻译： 描述与处理器的动态热响应的确定性管理有关的方法和装置。 在一个实施例中，可用的热余量可用于以确定性方式提取性能潜力，例如使其减少甚至消除产品与产品的变化。 还公开并要求保护其他实施例。

公开(公告)号：US20100115304A1

公开(公告)日：2010-05-06

申请号：US12263421

申请日：2008-10-31

申请人： Lev Finkelstein ,  Efraim Rotem ,  Aviad Cohen ,  Ronny Ronen ,  Doron Rajwan

发明人： Lev Finkelstein ,  Efraim Rotem ,  Aviad Cohen ,  Ronny Ronen ,  Doron Rajwan

IPC分类号： G06F1/32 ,  G06F1/00

CPC分类号： G06F1/26 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

摘要： Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed.

摘要翻译： 描述与多个处理器核心的电源管理相关的方法和装置。 在一个实施例中，本地可以利用一个或多个技术（例如，基于每个核心）来管理处理器中的功率消耗。 在另一个实施例中，功率可以基于能量考虑而分布在处理器的不同功率层之间。 还公开并要求保护其他实施例。

公开(公告)号：US20190004582A1

公开(公告)日：2019-01-03

申请号：US15635307

申请日：2017-06-28

申请人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

发明人： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC分类号： G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3296

摘要： In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US20170371401A1

公开(公告)日：2017-12-28

申请号：US15190417

申请日：2016-06-23

申请人： Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nir Rosenzweig ,  Eric Distefano ,  Ishmael F. Santos ,  James G. Hermerding, II

发明人： Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nir Rosenzweig ,  Eric Distefano ,  Ishmael F. Santos ,  James G. Hermerding, II

IPC分类号： G06F1/32 ,  G06F9/30

CPC分类号： G06F1/3296 ,  G06F1/3228 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3851

摘要： In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

公开(公告)号：US09652018B2

公开(公告)日：2017-05-16

申请号：US13997200

申请日：2011-12-30

申请人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

发明人： Efraim Rotem ,  Nir Rosenzweig ,  Doron Rajwan ,  Alon Naveh ,  Eliezer Weissmann

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/3203

摘要： Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types. Other embodiments are also disclosed and claimed.

公开(公告)号：US20150355705A1

公开(公告)日：2015-12-10

申请号：US14298171

申请日：2014-06-06

申请人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

发明人： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

摘要： In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括多个核心和功率控制器。 功率控制器可以包括硬件占空比（HDC）逻辑，以便即使逻辑处理器具有要执行的工作负载来使得一个核的至少一个逻辑处理器进入强制空闲状态。 此外，如果至少另外一个其他逻辑处理器被阻止进入强制空闲状态，则HDC逻辑可以导致逻辑处理器在空闲周期结束之前退出强制空闲状态。 描述和要求保护其他实施例。