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公开(公告)号：US20120086589A1
公开(公告)日：2012-04-12
申请号：US12899205
申请日：2010-10-06
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
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22.发明授权Chip to dielectric waveguide interface for sub-millimeter wave communications link 有权芯片到介质波导接口用于亚毫米波通信链路公开(公告)号：US09123737B2
公开(公告)日：2015-09-01
申请号：US12887323
申请日：2010-09-21
申请人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
发明人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
CPC分类号： H01Q3/44 , H01L23/3107 , H01L23/66 , H01L24/16 , H01L24/48 , H01L24/49 , H01L2223/6677 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2924/00014 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/3011 , H01Q3/26 , H01Q9/0407 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
摘要翻译： 在一些开发的互连技术中，例如芯片到芯片的光学互连或金属波导互连，错位可能是一个严重的问题。 然而，这里提供了使用片上定向天线（其在亚毫米范围内操作）通过介质波导形成射频（RF）互连的互连。 该系统允许不对准，同时提供增加的通信带宽。
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公开(公告)号：US20130265733A1
公开(公告)日：2013-10-10
申请号：US13439621
申请日：2012-04-04
CPC分类号： G02B6/12004 , G02B6/1228 , G02B6/43 , H01L2223/6627 , H01L2224/16227 , H01L2924/15311 , H01P3/16 , H01P5/107 , H05K1/0239 , H05K1/0243 , H05K1/025 , H05K1/0274 , H05K2201/0187 , H05K2201/037 , H05K2201/09618 , H05K2201/10098
摘要： An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
摘要翻译： 提供了一种装置。 存在具有封装基板和集成电路（IC）的电路组件。 封装衬底具有微带线，并且IC被固定到封装衬底并且电耦合到微带线。 电路板也固定到封装衬底。 介质波导固定在电路板上。 电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域的介质芯，并且微带线被配置为与介质波导形成通信链路。
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公开(公告)号：US09070703B2
公开(公告)日：2015-06-30
申请号：US12887270
申请日：2010-09-21
申请人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
发明人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
CPC分类号： H01L23/66 , H01L25/105 , H01L2223/6677 , H01L2224/48247 , H01L2225/1005 , H01L2924/3011 , H01L2924/00
摘要： In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
摘要翻译： 在一些开发的互连技术中，例如芯片到芯片的光学互连或金属波导互连，错位可能是一个严重的问题。 然而，这里提供了使用片上定向天线（其在亚毫米范围内操作）通过介质波导形成射频（RF）互连的互连。 该系统允许不对准，同时提供增加的通信带宽。
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公开(公告)号：US08284085B2
公开(公告)日：2012-10-09
申请号：US12899205
申请日：2010-10-06
IPC分类号： H03M3/00
摘要： Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.
摘要翻译： 传统上，流水线连续时间（CT）Σ-Δ调制器（SDM）已经难以构建，至少部分是由于校准管道的困难。 然而，这里提供了一种流水线CT SDM，其具有有助于被校准的架构。 也就是说，该系统包括数字滤波器和其他可调整的特征，以解决输入不平衡误差以及量化泄漏噪声。
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公开(公告)号：US20120068890A1
公开(公告)日：2012-03-22
申请号：US12887270
申请日：2010-09-21
申请人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
发明人： Baher S. Haroun , Marco Corsi , Siraj Akhtar , Nirmal C. Warke
CPC分类号： H01L23/66 , H01L25/105 , H01L2223/6677 , H01L2224/48247 , H01L2225/1005 , H01L2924/3011 , H01L2924/00
摘要： In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.
摘要翻译： 在一些开发的互连技术中，例如芯片到芯片的光学互连或金属波导互连，错位可能是一个严重的问题。 然而，这里提供了使用片上定向天线（其在亚毫米范围内操作）通过介质波导形成射频（RF）互连的互连。 该系统允许不对准，同时提供增加的通信带宽。
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公开(公告)号：US20110199972A1
公开(公告)日：2011-08-18
申请号：US13026777
申请日：2011-02-14
申请人： Nirmal Chindhu Warke , Srinath Hosur , Martin J. Izzard , Siraj Akhtar , Baher S. Haroun , Marco Corsi
发明人： Nirmal Chindhu Warke , Srinath Hosur , Martin J. Izzard , Siraj Akhtar , Baher S. Haroun , Marco Corsi
IPC分类号： H04W40/00
CPC分类号： H04W40/00 , H01Q3/26 , H01Q9/20 , H01Q21/0006 , H01Q21/0037 , H04B7/0617 , H04B17/336 , H04L45/74 , H04L49/3009 , H04L49/40 , H04W40/06 , H04W40/12 , Y02D70/00 , Y02D70/166 , Y02D70/322 , Y02D70/34
摘要： Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface.
摘要翻译： 本发明的实施例提供了一种用于电子电路中芯片到芯片通信的系统和方法。 路由器或交换机在输入端口ASIC处接收数据包。 输入端口ASIC或路由ASIC上的路由表用于根据数据包中的报头信息识别目标端口ASIC。 使用在波导或无线接口上传输的毫米波信号，将数据分组从输入端口ASIC发送到目标端口ASIC。
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28.发明授权Semiconductor device having wafer level chip scale packaging substrate decoupling 有权具有晶圆级芯片级封装衬底去耦的半导体器件公开(公告)号：US07919860B2
公开(公告)日：2011-04-05
申请号：US12048294
申请日：2008-03-14
IPC分类号： H01L23/48
CPC分类号： H01L23/3114 , H01L23/5223 , H01L23/525 , H01L24/11 , H01L24/12 , H01L2224/02313 , H01L2224/0401 , H01L2224/0558 , H01L2224/05624 , H01L2224/16 , H01L2924/14 , H01L2924/19041 , H01L2924/19104
摘要： One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.
摘要翻译： 本发明的一个方面提供一种包括具有最外表面的微芯片的半导体器件。 第一和第二接合焊盘位于微芯片上并且在最外表面附近。 第一UBM触点位于最外表面和第一和第二接合焊盘之间。 第一个UBM触点与第一个焊盘相抵消。 第二UBM触点位于最外表面上以及第一和第二接合焊盘之间。 第二UBM触点偏离第二接合焊盘，并且由微芯片支撑的电容器位于第一和第二UBM触点之间。
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29.发明申请TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS 有权用于IEEE 1149.1测试访问端口的多个光纤扫描接入的TAP和链接模块公开(公告)号：US20100162061A1
公开(公告)日：2010-06-24
申请号：US12539373
申请日：2009-08-11
申请人： Baher S. Haroun , Lee D. Whetsel
发明人： Baher S. Haroun , Lee D. Whetsel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G11C29/46
摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
摘要翻译： 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。
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30.发明授权TAP and linking module for scan access of multiple cores with IEEE 1149.1 test access ports 有权TAP和连接模块，用于具有IEEE 1149.1测试访问端口的多个核心的扫描访问公开(公告)号：US06324662B1
公开(公告)日：2001-11-27
申请号：US09277504
申请日：1999-03-26
申请人： Baher S. Haroun , Lee D. Whetsel
发明人： Baher S. Haroun , Lee D. Whetsel
IPC分类号： G01R3128
CPC分类号： G01R31/318536 , G01R31/318555 , G01R31/318563
摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
摘要翻译： 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。
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