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43 条记录 (耗时 0.033 秒)

    Method of producing an interconnect structure for an integrated circuit
    23.
    发明授权
    Method of producing an interconnect structure for an integrated circuit 失效

    公开(公告)号：US06548396B2

    公开(公告)日：2003-04-15

    申请号：US09874874

    申请日：2001-06-05

    申请人： Mehul Naik ,  Samuel Broydo

    发明人： Mehul Naik ,  Samuel Broydo

    IPC分类号： H01L214763

    CPC分类号： H01L21/76808

    摘要： A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.

    Integrated CVD/PVD Al planarization using ultra-thin nucleation layers
    24.
    发明授权
    Integrated CVD/PVD Al planarization using ultra-thin nucleation layers 失效
    使用超薄成核层的集成CVD / PVD ​​Al平面化

    公开(公告)号：US6139905A

    公开(公告)日：2000-10-31

    申请号：US838839

    申请日：1997-04-11

    申请人： Liang-Yuh Chen ,  Mehul Naik ,  Ted Guo ,  Roderick Craig Mosely

    发明人： Liang-Yuh Chen ,  Mehul Naik ,  Ted Guo ,  Roderick Craig Mosely

    IPC分类号： H01L21/28 ,  H01L21/203 ,  H01L21/3205 ,  H01L21/768 ,  B05D5/12

    CPC分类号： H01L21/28556 ,  H01J37/32082 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877

    摘要： The present invention provides a method and apparatus for forming an interconnect with application in small feature sizes (such as quarter micron widths) having high aspect ratios. Generally, the present invention provides a method and apparatus for depositing a wetting layer for subsequent physical vapor deposition to fill the interconnect. In one aspect of the invention, the wetting layer is a metal layer deposited using either CVD techniques or electroplating, such as CVD aluminum (Al). The wetting layer is nucleated using an ultra-thin layer, denoted as .di-elect cons. layer, as a nucleation layer. The .di-elect cons. layer is preferably comprised of a material such as Ti, TiN, Al, Ti/TiN, Ta, TaN, Cu, a flush of TDMAT or the like. The .di-elect cons. layer may be deposited using PVD or CVD techniques, preferably PVD techniques to improve film quality and orientation within the feature. Contrary to conventional wisdom, the .di-elect cons. layer is not continuous to nucleate the growth of the CVD wetting layer thereon. A PVD deposited metal is then deposited on the wetting layer at low temperature to fill the interconnect.

    摘要翻译： 本发明提供一种用于形成具有高纵横比的小特征尺寸（例如四分之一微米宽度）的互连的方法和装置。 通常，本发明提供了一种用于沉积用于后续物理气相沉积以润湿互连的润湿层的方法和装置。 在本发明的一个方面，润湿层是使用CVD技术或电镀（诸如CVD铝（Al））沉积的金属层。 润湿层使用表示为+531层的超薄层作为成核层成核。 +531层优选由诸如Ti，TiN，Al，Ti / TiN，Ta，TaN，Cu的材料，TDMAT等的齐平构成。 可以使用PVD或CVD技术沉积+531层，优选PVD技术以改善特征内的膜质量和取向。 与常规智慧相反，+531层不连续以使其上的CVD润湿层的生长成核。 然后在低温下将PVD沉积的金属沉积在润湿层上以填充互连。

    Methods and apparatus of creating airgap in dielectric layers for the reduction of RC delay
    26.
    发明授权
    Methods and apparatus of creating airgap in dielectric layers for the reduction of RC delay 有权
    在电介质层中产生气隙以减少RC延迟的方法和装置

    公开(公告)号：US07879683B2

    公开(公告)日：2011-02-01

    申请号：US11869396

    申请日：2007-10-09

    申请人： Amir Al-Bayati ,  Alexandros T. Demos ,  Kang Sub Yim ,  Mehul Naik ,  Zhenjiang “David” Cui ,  Mihaela Balseanu ,  Meiyee (Maggie Le) Shek ,  Li-Qun Xia

    发明人： Amir Al-Bayati ,  Alexandros T. Demos ,  Kang Sub Yim ,  Mehul Naik ,  Zhenjiang “David” Cui ,  Mihaela Balseanu ,  Meiyee (Maggie Le) Shek ,  Li-Qun Xia

    IPC分类号： H01L21/76

    CPC分类号： H01L21/7682 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

    摘要： A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.

    摘要翻译： 一种用于在互连结构的电介质材料中产生气隙的方法和装置。 一个实施例提供了一种用于形成半导体结构的方法，包括在衬底上沉积第一介电层，在第一介电层中形成沟槽，用导电材料填充沟槽，平坦化导电材料以暴露第一介电层， 在导电材料和暴露的第一电介质层上的阻挡膜，在介电阻挡膜上沉积硬掩模层，在介电阻挡膜和硬掩模层中形成图案，以暴露衬底的选定区域，氧化至少一部分 在衬底的选定区域中的第一介电层，去除第一电介质层的氧化部分以在导电材料周围形成反向沟槽，以及在反向沟槽中形成气隙，同时在反向沟槽中沉积第二电介质材料。

    Method of producing an interconnect structure for an integrated circuit
    30.
    发明授权
    Method of producing an interconnect structure for an integrated circuit 失效
    制造用于集成电路的互连结构的方法

    公开(公告)号：US06245662B1

    公开(公告)日：2001-06-12

    申请号：US09122080

    申请日：1998-07-23

    申请人： Mehul Naik ,  Samuel Broydo

    发明人： Mehul Naik ,  Samuel Broydo

    IPC分类号： H01L214763

    CPC分类号： H01L21/76808

    摘要： A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.

    摘要翻译： 双镶嵌技术，在一个步骤中形成完整的通孔。 具体地，该方法将第一绝缘体层沉积在衬底上，在第一绝缘体层上方的蚀刻停止层以及蚀刻停止层顶部的第二绝缘体层。 然后通过施加根据最终通孔或通孔的尺寸的位置显影和图案化的光致抗蚀剂形成通孔掩模。 此后，可以在单个步骤中，例如使用反应离子蚀刻来蚀刻第一绝缘体层，蚀刻停止层和第二绝缘体层。 通过这三层形成的孔具有最终通孔的直径。 此后，将沟槽掩模并蚀刻到第二绝缘体层中。 沟槽蚀刻被蚀刻停止层停止。 通孔和沟槽被金属化以形成互连结构。 可以重复该技术以创建多级互连结构。