公开(公告)号：US20120194242A1

公开(公告)日：2012-08-02

申请号：US13015595

申请日：2011-01-28

申请人： Yen-Yin Huang ,  Chih-Hsien Lin ,  Chauo-Min Chen ,  Ming-Shih Yu

发明人： Yen-Yin Huang ,  Chih-Hsien Lin ,  Chauo-Min Chen ,  Ming-Shih Yu

IPC分类号： H03L7/24 ,  H03H11/26

CPC分类号： H03L7/0816 ,  H03K5/133 ,  H03K5/135 ,  H03L7/0814

摘要： A signal delay apparatus, including: a period digitalization circuit, for digitalizing a period of a reference clock signal to generate a digitalized reference period; a delay control signal generator, for generating a delay control signal according to the digitalized reference period, a reference frequency and a required delay indicating signal; and a delay circuit, for delaying an input signal to generate an output signal according to the required delay control signal.

摘要翻译： 一种信号延迟装置，包括：周期数字化电路，用于对参考时钟信号的周期进行数字化以产生数字化参考周期; 延迟控制信号发生器，用于根据数字化参考周期产生延迟控制信号，参考频率和所需延迟指示信号; 以及延迟电路，用于根据所需的延迟控制信号延迟输入信号以产生输出信号。

公开(公告)号：US07897505B2

公开(公告)日：2011-03-01

申请号：US11727133

申请日：2007-03-23

申请人： Chung-Chi Ko ,  Lih-Ping Li ,  Yung-Cheng Lu ,  Hui-Lin Chang ,  Chih-Hsien Lin

发明人： Chung-Chi Ko ,  Lih-Ping Li ,  Yung-Cheng Lu ,  Hui-Lin Chang ,  Chih-Hsien Lin

IPC分类号： H01L21/4763 ,  H01L21/00

CPC分类号： H01L21/31633 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835

摘要： A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.

摘要翻译： 一种新颖的方法，用于在半导体晶片衬底上的集成电路制造过程中，在金属互连的形成过程中，增强相邻电介质层之间的界面附着力，特别是在蚀刻停止层和具有低介电常数（k）的上覆电介质层之间。 该方法可以包括提供衬底，在衬底上提供蚀刻停止层，在蚀刻停止层上提供富氧介电预置层，并在富氧电介质预层上提供主要电介质层。 然后在电介质层中形成金属互连。 在蚀刻停止层和上部电介质层之间的富氧介电预层防止或最小化由金属层和/或芯片封装的化学机械平坦化引起的应力引起的层的剥离和破裂。

公开(公告)号：US20080032472A1

公开(公告)日：2008-02-07

申请号：US11524000

申请日：2006-09-20

申请人： Chen-Hua Yu ,  Ming-Shih Yeh ,  Chih-Hsien Lin ,  Yung-Cheng Lu ,  Hui-Lin Chang

发明人： Chen-Hua Yu ,  Ming-Shih Yeh ,  Chih-Hsien Lin ,  Yung-Cheng Lu ,  Hui-Lin Chang

IPC分类号： H01L21/8242

CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/76826

摘要： A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.

摘要翻译： 形成集成电路的方法包括提供半导体衬底，在半导体衬底上形成金属化层，其中金属化层包括低k电介质层中的金属特征并且从低k电介质层的顶表面延伸 进入低k电介质层，对低k电介质层进行处理以形成亲水性顶表面，以及在溶液中的金属特征上镀覆盖层。

公开(公告)号：US06798950B2

公开(公告)日：2004-09-28

申请号：US10170423

申请日：2002-06-14

申请人： Sheng-Jui Chao ,  Chih-Hsien Lin ,  Yuan-Kai Liu

发明人： Sheng-Jui Chao ,  Chih-Hsien Lin ,  Yuan-Kai Liu

IPC分类号： G02B632

CPC分类号： G02B6/32 ,  G02B6/4225 ,  G02B6/4226 ,  G02B6/4227

摘要： The present invention relates to an instrument and method of aligning a collimator. The instrument includes a frame base, a clamp, a first axis stage, a second axis stage, and a rack. A ferrule grasping a fiber therein is inserted in a glass tube, and the glass tube is secured to the frame base by the clamp. A pinion is fixedly mounted on one end of a GRIN lens, which is inserted in the glass tube, and engaged with the rack. The first axis stage moves the GRIN lens along the cylindrical axis of the glass tube, and the second axis stage rotates the GRIN lens around the cylindrical axis of the glass tube. When a light beam emitted from the collimator reaches the maximum intensity, the instrument of the invention accomplishes the alignment of the collimator.

摘要翻译： 本发明涉及一种对准准直仪的仪器和方法。 该仪器包括框架基座，夹具，第一轴台，第二轴台和架。 将其中夹持纤维的套圈插入玻璃管中，并且玻璃管通过夹具固定到框架基座。 小齿轮固定地安装在GRIN透镜的一端，该GRIN透镜插入玻璃管中并与机架接合。 第一轴台沿着玻璃管的圆柱轴移动GRIN透镜，第二轴台将GRIN透镜绕玻璃管的圆柱轴线旋转。 当从准直器发射的光束达到最大强度时，本发明的仪器实现了准直仪的对准。

公开(公告)号：US06436787B1

公开(公告)日：2002-08-20

申请号：US09912735

申请日：2001-07-26

申请人： Wong-Cheng Shih ,  Tzyh-Cheang Lee ,  Wenchi Ting ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

发明人： Wong-Cheng Shih ,  Tzyh-Cheang Lee ,  Wenchi Ting ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

IPC分类号： H01L2120

CPC分类号： H01L28/55 ,  H01L21/3212 ,  H01L28/75 ,  H01L28/91

摘要： A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper damascene process is described. A contact node is provided overlying a semiconductor substrate. An intermetal dielectric layer is deposited overlying the contact node. A damascene opening is formed through the intermetal dielectric layer to the contact node. A first metal layer is formed on the bottom and sidewalls of the damascene opening and overlying the intermetal dielectric layer. A first barrier metal layer is is deposited overlying the first metal layer. A dielectric layer is dpeosited overlying the first barrier metal layer. A second barrier metal layer is deposited overlying the dielectric layer. A second metal layer is formed overlying the second barrier metal layer and completely filling the damascene opening. The layers are polished back to leave the first metal layer, the dielectric layer, the first and second barrier metal layers, and the second metal layer only within the damascene opening wherein the first metal layer forms a bottom electrode, the dielectric layer forms a capacitor dielectric, and the second metal layer forms a top electrode to complete fabrication of a crown-type capacitor in the fabrication of an integrated circuit device.

摘要翻译： 描述了使用集成铜镶嵌工艺制造增加的电容金属 - 绝缘体 - 金属电容器的方法。 提供覆盖半导体衬底的接触节点。 沉积在接触节点上的金属间介电层。 通过金属间介质层向接触节点形成镶嵌开口。 第一金属层形成在镶嵌开口的底部和侧壁上并覆盖金属间介电层。 第一阻挡金属层被沉积​​在第一金属层上。 介电层被覆在第一阻挡金属层上方。 沉积在电介质层上的第二阻挡金属层。 形成第二金属层，覆盖第二阻挡金属层并完全填充镶嵌开口。 这些层被抛光回去，以留下第一金属层，电介质层，第一和第二阻挡金属层和第二金属层，仅在镶嵌开口内，其中第一金属层形成底部电极，电介质层形成电容器 电介质，并且第二金属层形成顶部电极，以在集成电路器件的制造中完成冠型电容器的制造。

公开(公告)号：US08711558B2

公开(公告)日：2014-04-29

申请号：US13157687

申请日：2011-06-10

申请人： Fa-Chih Ke ,  Chih-Hsien Lin

发明人： Fa-Chih Ke ,  Chih-Hsien Lin

IPC分类号： G06F1/16

CPC分类号： G06F1/16 ,  G06F1/1616 ,  G06F1/1662 ,  G06F1/1669 ,  Y10T292/084

摘要： An electronic device includes a case, a plate, and a detachable member. The case has a first receiving area, a second receiving area, and a movable latch. The first receiving area is adjacent to the second receiving area. The movable latch moves back and forth between the first receiving area and the second receiving area. The detachable member is assembled to the first receiving area. The plate is assembled to the second receiving area. When the movable latch is located in the first receiving area, the movable latch locks the detachable member to the case. When the movable latch moves to the second receiving area, the movable latch is locked to the plate.

摘要翻译： 电子设备包括壳体，板和可拆卸构件。 壳体具有第一接收区域，第二接收区域和可移动闩锁。 第一接收区域与第二接收区域相邻。 可移动闩锁在第一接收区域和第二接收区域之间来回移动。 可拆卸构件组装到第一接收区域。 板被组装到第二接收区域。 当可移动闩锁位于第一接收区域中时，可移动闩锁将可拆卸构件锁定到壳体。 当可动闩锁移动到第二接收区域时，可移动闩锁被锁定到板上。

公开(公告)号：US20120298410A1

公开(公告)日：2012-11-29

申请号：US13118129

申请日：2011-05-27

申请人： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Wei-Sho Hung

发明人： Hsiang-Tai Lu ,  Chih-Hsien Lin ,  Wei-Sho Hung

IPC分类号： H05K1/11 ,  H05K3/34

CPC分类号： H01L23/49827 ,  H01L22/32 ,  H01L23/49822 ,  H01L2224/13025 ,  H01L2224/16

摘要： An interconnection component includes a substrate, and an active through-substrate via (TSV) penetrating through the substrate. Active metal connections are formed over the substrate and electrically connected to the active TSV. At least one of a dummy pad and a dummy solder bump are formed at surfaces of the interconnection component. The dummy pad is over the substrate and electrically connected to the active TSV and the active metal connections. The dummy solder bump is under the substrate and electrically connected to the active metal connections. The dummy pad and the dummy solder bump are open ended.

摘要翻译： 互连部件包括基板和穿透基板的有源贯穿基板通孔（TSV）。 有源金属连接形成在基板上并电连接到有源TSV。 在互连部件的表面形成虚拟焊盘和虚拟焊料凸点中的至少一个。 虚拟焊盘在基板上，并电连接到有源TSV和有源金属连接。 虚拟焊料凸块位于基板之下并电连接到有源金属连接。 虚拟焊盘和虚拟焊料凸块是开放式的。

公开(公告)号：US20120290117A1

公开(公告)日：2012-11-15

申请号：US13107401

申请日：2011-05-13

申请人： Jane-Yau Wang ,  Chih-Chung Chen ,  Chih-Hsien Lin

发明人： Jane-Yau Wang ,  Chih-Chung Chen ,  Chih-Hsien Lin

IPC分类号： H01L21/02

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming indicia on a semiconductor device package, such as laser marked or ink stamp marked indicia. The method can be performed on an apparatus, such as a production apparatus, which forms the indicia as well as performs semiconductor device trim and form operations. An embodiment of the present teachings ensures that the indicia marking process at a laser marking station does not occur simultaneously with the device trim and form operations at a trim and form station. Trim and form operations, particularly using a ram press, can impose vibrations on the laser marking station. Ensuring that laser marking does not occur simultaneously with trim and form operations removes the negative effects of vibration on the laser marking station.

摘要翻译： 一种用于在半导体器件封装上形成标记的方法，例如激光标记或墨水标记的标记。 该方法可以在形成标记的设备，例如生产设备上执行，并且执行半导体器件修整和形成操作。 本教导的一个实施例确保了在激光打标站处的标记标记过程不与设备修剪同时进行，并且在修剪和成型台处形成操作。 修剪和成型操作，特别是使用冲压机，可以在激光打标台上施加振动。 确保激光打标不会与修剪和成形操作同时发生，从而消除激光打标台上振动的负面影响。

公开(公告)号：US08242824B1

公开(公告)日：2012-08-14

申请号：US13015595

申请日：2011-01-28

申请人： Yen-Yin Huang ,  Chih-Hsien Lin ,  Chauo-Min Chen ,  Ming-Shih Yu

发明人： Yen-Yin Huang ,  Chih-Hsien Lin ,  Chauo-Min Chen ,  Ming-Shih Yu

IPC分类号： H03L7/00

CPC分类号： H03L7/0816 ,  H03K5/133 ,  H03K5/135 ,  H03L7/0814

摘要： A signal delay apparatus, including: a period digitalization circuit, for digitalizing a period of a reference clock signal to generate a digitalized reference period; a delay control signal generator, for generating a delay control signal according to the digitalized reference period, a reference frequency and a required delay indicating signal; and a delay circuit, for delaying an input signal to generate an output signal according to the required delay control signal.

摘要翻译： 一种信号延迟装置，包括：周期数字化电路，用于对参考时钟信号的周期进行数字化以产生数字化参考周期; 延迟控制信号发生器，用于根据数字化参考周期产生延迟控制信号，参考频率和所需延迟指示信号; 以及延迟电路，用于根据所需的延迟控制信号延迟输入信号以产生输出信号。

公开(公告)号：US07639801B2

公开(公告)日：2009-12-29

申请号：US11096957

申请日：2005-03-31

申请人： Shyh-Jye Jou ,  Chih-Ning Chen ,  You-Jiun Wang ,  Ju-Yuan Hsiao ,  Chih-Hsien Lin

发明人： Shyh-Jye Jou ,  Chih-Ning Chen ,  You-Jiun Wang ,  Ju-Yuan Hsiao ,  Chih-Hsien Lin

IPC分类号： H04L9/00

CPC分类号： H03K3/356156 ,  H04B2201/70707

摘要： A method of transforming a serial scrambler to a parallel scrambler, a parallel scrambler and a double-edge-triggered register with XOR operation are provided. The method transforms a serial scrambler to a parallel scrambler according to a characteristic polynomial: P ⁡ ( x ) = ∑ q = 0 N ⁢ c q ⁢ x q ⁢ ⁢ or ⁢ ⁢ b ⁡ ( i ) = ∑ q = 1 N ⁢ c q ⁢ b ⁡ ( i - q ) . The method first determines a transformation formula: b ⁡ ( kN + i ) = ∑ q = 1 N ⁢ c q ⁢ b ⁡ ( ( k - R ) ⁢ N + i + R ⁡ ( N - q ) ) according to the parameters of the characteristic polynomial. The parallel bits Bj=[bMj, bMj+1, . . . , bMj+M−2, bMj+M−1] are arranged in order. The transformation number R=2t (the initial number of t is 0) is set. The parallel bits are replaced by the transformation formula. When (k−R)N+i+R(N−q) is larger than Mj−1 in the transformation formula, 1 is added to t in the transformation formula R=2t and the transformation formula is re-counted. Finally, the XOR gates are connected to the registers according to a computed result from the transformation formula.

摘要翻译： 提供了一种将串行加扰器变换为并行扰频器，并行扰频器和具有异或运算的双边沿触发寄存器的方法。 该方法根据特征多项式将串扰扰码器转换为并行扰频器：P⁡（x）=Σq = 0 N cq xq ud或⁢b⁡（i）=Σq = 1 N cq b⁡（i-q）。 该方法首先根据下列参数确定变换公式：b⁡（kN + i）=Σq = 1 N cq b⁡（（k-R）N + i + R⁡（N-q） 特征多项式。 并行位Bj = [bMj，bMj + 1，... 。 。 ，bMj + M-2，bMj + M-1]。 转换数R = 2t（t的初始数为0）被设置。 并行位由变换公式代替。 当变换式中（k-R）N + i + R（N-q）大于Mj-1时，在转化公式R = 2t中加入1，转化公式重新计算。 最后，XOR门根据转换公式的计算结果连接到寄存器。