Method for enhancing adhesion between layers
    1.
    发明申请
    Method for enhancing adhesion between layers 有权
    提高层间粘附性的方法

    公开(公告)号:US20080233765A1

    公开(公告)日:2008-09-25

    申请号:US11727133

    申请日:2007-03-23

    IPC分类号: H01L21/469 H01L21/31

    摘要: A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.

    摘要翻译: 一种新颖的方法,用于在半导体晶片衬底上的集成电路制造过程中,在金属互连的形成过程中,增强相邻电介质层之间的界面附着力,特别是在蚀刻停止层和具有低介电常数(k)的上覆电介质层之间。 该方法可以包括提供衬底,在衬底上提供蚀刻停止层,在蚀刻停止层上提供富氧介电预置层,并在富氧电介质预层上提供主要电介质层。 然后在电介质层中形成金属互连。 在蚀刻停止层和上部电介质层之间的富氧介电预层防止或最小化由金属层和/或芯片封装的化学机械平坦化引起的应力引起的层的剥离和破裂。

    Method for enhancing adhesion between layers in BEOL fabrication
    2.
    发明授权
    Method for enhancing adhesion between layers in BEOL fabrication 有权
    增加BEOL制作中层间粘附性的方法

    公开(公告)号:US07897505B2

    公开(公告)日:2011-03-01

    申请号:US11727133

    申请日:2007-03-23

    IPC分类号: H01L21/4763 H01L21/00

    摘要: A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.

    摘要翻译: 一种新颖的方法,用于在半导体晶片衬底上的集成电路制造过程中,在金属互连的形成过程中,增强相邻电介质层之间的界面附着力,特别是在蚀刻停止层和具有低介电常数(k)的上覆电介质层之间。 该方法可以包括提供衬底,在衬底上提供蚀刻停止层,在蚀刻停止层上提供富氧介电预置层,并在富氧电介质预层上提供主要电介质层。 然后在电介质层中形成金属互连。 在蚀刻停止层和上部电介质层之间的富氧介电预层防止或最小化由金属层和/或芯片封装的化学机械平坦化引起的应力引起的层的剥离和破裂。

    Method for ultra low-K dielectric deposition
    8.
    发明申请
    Method for ultra low-K dielectric deposition 审中-公开
    超低K电介质沉积方法

    公开(公告)号:US20050048795A1

    公开(公告)日:2005-03-03

    申请号:US10649566

    申请日:2003-08-27

    摘要: The present invention provides a method of forming a semiconductor structure having an ultra low-K dielectric material that adheres well to the substrate. The method includes depositing a low-K material on the top surface of a substrate at a low temperature of no more than 250° by a CVD or spin-on process. The dielectric material is then cured by placing the substrate with the dielectric film in an environment where the temperature is regulated at about 400° or less as the dielectric film is being subjected to a plasma treatment or an E-beam treatment or UV treatment. The environment may further include one or more gases or a mixture of gases selected from the group consisting of H2, N2, NH3, CO2, all hydride gases and a mixture of these gases.

    摘要翻译: 本发明提供一种形成半导体结构的方法,所述半导体结构具有与基底良好粘合的超低K电介质材料。 该方法包括通过CVD或旋涂工艺在低于250°的低温下在衬底的顶表面上沉积低K材料。 然后通过将介质膜放置在介质膜经受等离子体处理或电子束处理或UV处理的温度调节在约400°或更小的环境中来固化电介质材料。 环境可以进一步包括选自H 2,N 2,NH 3,CO 2,所有氢化物气体和这些气体的混合物的一种或多种气体或气体混合物。

    Methods for improving uniformity of cap layers
    9.
    发明申请
    Methods for improving uniformity of cap layers 有权
    改善盖层均匀性的方法

    公开(公告)号:US20080032472A1

    公开(公告)日:2008-02-07

    申请号:US11524000

    申请日:2006-09-20

    IPC分类号: H01L21/8242

    摘要: A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.

    摘要翻译: 形成集成电路的方法包括提供半导体衬底,在半导体衬底上形成金属化层,其中金属化层包括低k电介质层中的金属特征并且从低k电介质层的顶表面延伸 进入低k电介质层,对低k电介质层进行处理以形成亲水性顶表面,以及在溶液中的金属特征上镀覆盖层。