公开(公告)号：US20060081875A1

公开(公告)日：2006-04-20

申请号：US10967917

申请日：2004-10-18

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC分类号： H01L31/109 ,  H01L31/0328 ,  H01L29/76

CPC分类号： H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802

摘要： A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.

摘要翻译： 晶体管结构包括覆盖衬底区域的沟道区域。 衬底区域包括具有第一晶格常数的第一半导体材料。 沟道区域包括具有第二晶格常数的第二半导体材料。 源极区和漏极区相对地邻近沟道区，并且源极和漏极区的顶部包括第一半导体材料。 栅极电介质层覆盖沟道区，栅电极覆盖在栅介质层上。

公开(公告)号：US20050272188A1

公开(公告)日：2005-12-08

申请号：US11201990

申请日：2005-08-11

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L31/109

CPC分类号： H01L29/1054 ,  H01L21/84 ,  H01L27/1203

摘要： A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile strain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

摘要翻译： 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于覆盖SiGe层的硅层中，允许NMOS沟道区存在于双层拉伸应变增强下的硅层中 电子迁移率。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

公开(公告)号：US20050156208A1

公开(公告)日：2005-07-21

申请号：US10955349

申请日：2004-09-30

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/665 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/785

摘要： Provided are a semiconductor device and a method for its fabrication. In one example, the semiconductor device includes an active region formed on a substrate using a first silicide type and another active region formed on the substrate using another silicide type. The two silicide types differ and at least one of the two silicides is an alloy silicide. An etch stop layer may overlay at least one of the silicide regions.

摘要翻译： 提供半导体器件及其制造方法。 在一个示例中，半导体器件包括使用第一硅化物类型形成在衬底上的有源区和使用另一种硅化物类型形成在衬底上的另一有源区。 两种硅化物类型不同，并且两种硅化物中的至少一种是合金硅化物。 蚀刻停止层可覆盖至少一个硅化物区域。

公开(公告)号：US20050009263A1

公开(公告)日：2005-01-13

申请号：US10730778

申请日：2003-12-09

申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Hu

发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Chen Hu

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

摘要： A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.

公开(公告)号：US06812116B2

公开(公告)日：2004-11-02

申请号：US10318454

申请日：2002-12-13

申请人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Kuo-Nan Yang ,  Chun-Chieh Lin ,  Chenming Hu

发明人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Kuo-Nan Yang ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L21301

CPC分类号： H01L21/3247 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/324 ,  H01L21/76259 ,  H01L29/1054

摘要： A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1−x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1−x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.

摘要翻译： 实现了制造具有用于增加电子和空穴迁移率的应变硅层的SOI晶片的方法。 该方法在种子晶片上形成多孔硅层。 使用H2退火在多孔硅上形成光滑表面。 沉积无应变的（松弛的）外延六面体Ge-x层并形成结合层。 然后将种子晶片结合到在表面上具有绝缘体的手柄晶片。 使用喷涂蚀刻来蚀刻多孔Si层，导致SOI处理晶片，其具有在松弛的SixGe1-x上的多孔Si层的部分。 然后将处理晶片在H 2中退火以将多孔Si转化为SOI晶片的松弛SiGe层上的平滑应变Si层。

公开(公告)号：US09673280B2

公开(公告)日：2017-06-06

申请号：US11714416

申请日：2007-03-06

申请人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

发明人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L29/10 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L29/1054 ,  H01L21/02142 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834

摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

公开(公告)号：US20060255365A1

公开(公告)日：2006-11-16

申请号：US11483913

申请日：2006-07-10

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L31/00

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

摘要： A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

公开(公告)号：US20060220119A1

公开(公告)日：2006-10-05

申请号：US11423457

申请日：2006-06-12

申请人： Chun-Chieh Lin ,  Yee-Chia Yeo

发明人： Chun-Chieh Lin ,  Yee-Chia Yeo

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/823425 ,  H01L21/76224 ,  H01L21/823412 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7848

摘要： A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

摘要翻译： 应变通道半导体结构及其制造方法。 应变通道半导体结构包括由具有第一自然晶格常数的第一半导体材料构成的衬底。 沟道区设置在衬底中，并且栅堆叠设置在应变沟道区上方，一对源极/漏极区相对地设置在与沟道区相邻的衬底中，其中源/漏区中的每一个包括晶格 - 错配区域包括具有第二自然晶格常数而不是第一自然晶格常数的第二半导体材料，对应于栅极堆叠的内侧和外侧，并且至少一个外侧横向接触基板的第一半导体材料。

公开(公告)号：US07112495B2

公开(公告)日：2006-09-26

申请号：US10729095

申请日：2003-12-05

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

摘要： A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

摘要翻译： 半导体芯片包括其中设置有第一和第二有源区的半导体衬底126。 电阻器124形成在第一有源区域中，并且电阻器124包括形成在两个端子136之间的掺杂区域128。 应变通道晶体管132形成在第二有源区中。 该晶体管包括第一和第二应力源141，该第一和第二应力器141形成在与基片相反的相邻的应变通道区域143之间。

公开(公告)号：US20060177997A1

公开(公告)日：2006-08-10

申请号：US11377105

申请日：2006-03-16

申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

IPC分类号： H01L21/20

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.

摘要翻译： 提供一种制造集成电路的方法。 第一栅介质部分形成在第一晶体管区域中的衬底上。 第一栅介质部分包括第一高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 在第二晶体管区域中的衬底上形成第二栅介质部分。 第二栅介质部分包括第一高电容率介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度不同于第一等效氧化硅厚度。