公开(公告)号：US20100283136A1

公开(公告)日：2010-11-11

申请号：US12840304

申请日：2010-07-21

申请人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

发明人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49586 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a third wire bonding the intermediary terminal to the extended, outer terminal lead.

摘要翻译： QFN半导体封装包括管芯附接垫; 安装在管芯附接垫上的半导体管芯; 设置在所述管芯附接垫附近的内部端子引线; 将内端子引线接合到半导体管芯的第一引线; 延伸的外部端子引线，设置在所述QFN半导体封装的周围，其中所述延伸的外部端子引线设置在超过半导体管芯上的特定最小焊盘开口尺寸的最大焊丝长度之上; 设置在内端子引线和延伸外端子引线之间的中间端子; 将所述中间端子连接到所述半导体管芯的第二引线; 以及将中间终端连接到扩展的外部终端引线的第三引线。

公开(公告)号：US07561481B2

公开(公告)日：2009-07-14

申请号：US11760955

申请日：2007-06-11

申请人： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

发明人： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

IPC分类号： G11C7/00

CPC分类号： G06F13/1694

摘要： Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.

摘要翻译： 提供了存储器控制器及其优化焊盘序列的方法。 首先提供用于至少一个存储器件的印刷电路板上的至少两个不同的优选迹线序列。 然后提供一个存储器控制器以具有核心逻辑电路，多个输入/输出（I / O）设备和重新启动器。 核心逻辑有I / O端子。 单个芯片上的每个I / O设备都有一个焊盘。 重排器耦合在核心逻辑电路和输入/输出设备之间，可编程以将输入/输出设备选择性地连接到输入/输出端子。 后续程序随后被编程为选择并将输入/输出设备的一部分连接到输入/输出端子，使得基本上支持不同优选轨迹序列之一。

公开(公告)号：US20080080142A1

公开(公告)日：2008-04-03

申请号：US11763630

申请日：2007-06-15

申请人： Nan-Cheng Chen ,  Chun-Wei Chang ,  Chao-Wei Tseng

发明人： Nan-Cheng Chen ,  Chun-Wei Chang ,  Chao-Wei Tseng

IPC分类号： H05K7/20

CPC分类号： H05K7/205 ,  H05K1/0203 ,  H05K1/0204 ,  H05K1/0206 ,  H05K3/341 ,  H05K3/3452 ,  H05K2201/0715 ,  H05K2201/09054 ,  H05K2201/10303 ,  H05K2201/10477 ,  H05K2201/10727

摘要： An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer.

摘要翻译： 具有增强散热性的电子设备。 印刷电路板设置在壳体中，并且包括第一金属接地层，第二金属接地层和金属连接部分。 第一金属接地层与第二金属接地层相对。 金属连接部分连接在第一和第二金属接地层之间。 第二金属接地层连接到外壳。 芯片电连接到印刷电路板，并且包括模具和连接到模具并与第一金属接地层焊接的导热部分。 由芯片产生的热量通过导热部分，第一金属接地层，金属连接部分和第二金属接地层传导到壳体。

公开(公告)号：US07786557B2

公开(公告)日：2010-08-31

申请号：US12390492

申请日：2009-02-22

申请人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

发明人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49586 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A quad flat non-lead (QFN) semiconductor package includes a die attach pad having a recessed area; a semiconductor die mounted inside the recessed area of the die attach pad; at least one row of inner terminal leads disposed adjacent to the die attach pad; first wires bonding respective said inner terminal leads to the semiconductor die; at least one row of extended, outer terminal leads disposed along periphery of the QFN semiconductor package; at least one row of intermediary terminals disposed between the inner terminal leads and the extended, outer terminal leads; second wires bonding respective the intermediary terminals to the semiconductor die; and third wires bonding respective the intermediary terminals to the extended, outer terminal leads.

摘要翻译： 四边形非引线（QFN）半导体封装包括具有凹陷区域的管芯附接焊盘; 安装在管芯附接垫的凹陷区域内的半导体管芯; 至少一列内部端子引线邻近管芯附接垫设置; 将所述内部端子引线分别连接到所述半导体管芯的第一引线; 至少一排沿QFN半导体封装的周边设置的延伸外端子引线; 设置在内部端子引线和延伸的外部端子引线之间的至少一排中间端子; 将所述中间端子分别连接到所述半导体管芯的第二配线; 以及将中间端子分别连接到扩展的外部端子引线的第三线。

公开(公告)号：US20090294938A1

公开(公告)日：2009-12-03

申请号：US12370537

申请日：2009-02-12

申请人： Nan-Cheng Chen

发明人： Nan-Cheng Chen

IPC分类号： H01L23/52 ,  H01L23/498

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5382 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

摘要： A flip-chip package includes a package carrier; a semiconductor die having a die face and a die edge, the semiconductor die being assembled face-down to a chip side of the package carrier, and contact pads are situated on the die face; a rewiring laminate structure between the semiconductor die and the package carrier, the rewiring laminate structure including a re-routed metal layer, and at least a portion of the re-routed metal layer projects beyond the die edge; and bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier.

摘要翻译： 倒装芯片封装包括封装载体; 具有裸片面和芯片边缘的半导体管芯，半导体管芯正面朝下装配到封装载体的芯片侧，接触焊盘位于管芯面上; 在半导体管芯和封装载体之间的重新布线的层压结构，重新布线层压结构包括重新布线的金属层，并且至少一部分重新布线的金属层突出超过管芯边缘; 以及布置在重新布线层压结构上的凸块，用于将半导体管芯与封装载体电连接。

公开(公告)号：US20090236707A1

公开(公告)日：2009-09-24

申请号：US12473477

申请日：2009-05-28

申请人： Nan-Cheng Chen ,  Chun-Wei Chang ,  Chao-Wei Tseng

发明人： Nan-Cheng Chen ,  Chun-Wei Chang ,  Chao-Wei Tseng

IPC分类号： H01L23/34 ,  H01L23/495 ,  H01L23/498 ,  H01L23/48

CPC分类号： H05K7/205 ,  H05K1/0203 ,  H05K1/0204 ,  H05K1/0206 ,  H05K3/341 ,  H05K3/3452 ,  H05K2201/0715 ,  H05K2201/09054 ,  H05K2201/10303 ,  H05K2201/10477 ,  H05K2201/10727

摘要： An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer.

摘要翻译： 具有增强散热性的电子设备。 印刷电路板设置在壳体中，并且包括第一金属接地层，第二金属接地层和金属连接部分。 第一金属接地层与第二金属接地层相对。 金属连接部分连接在第一和第二金属接地层之间。 第二金属接地层连接到外壳。 芯片电连接到印刷电路板，并且包括模具和连接到模具并与第一金属接地层焊接的导热部分。 由芯片产生的热量通过导热部分，第一金属接地层，金属连接部分和第二金属接地层传导到壳体。

公开(公告)号：US20080304352A1

公开(公告)日：2008-12-11

申请号：US11760955

申请日：2007-06-11

申请人： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

发明人： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

IPC分类号： G11C8/06

CPC分类号： G06F13/1694

摘要： Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.

摘要翻译： 提供了存储器控制器及其优化焊盘序列的方法。 首先提供用于至少一个存储器件的印刷电路板上的至少两个不同的优选迹线序列。 然后提供一个存储器控制器以具有核心逻辑电路，多个输入/输出（I / O）设备和重新启动器。 核心逻辑有I / O端子。 单个芯片上的每个I / O设备都有一个焊盘。 重排器耦合在核心逻辑电路和输入/输出设备之间，可编程以将输入/输出设备选择性地连接到输入/输出端子。 后续程序随后被编程为选择并将输入/输出设备的一部分连接到输入/输出端子，使得基本上支持不同优选轨迹序列之一。