公开(公告)号：US5770501A

公开(公告)日：1998-06-23

申请号：US577033

申请日：1995-12-22

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A process of fabricating a flash EEPROM having a NAND structure by using the liquid phase deposition (LPD) technique and self-alignment technique is disclosed to achieve higher density and reliability of flash memory cells and eliminating the shortcomings of the bird's beaks of field oxides.

摘要翻译： 公开了通过使用液相沉积（LPD）技术和自对准技术制造具有NAND结构的快闪EEPROM的工艺，以实现闪速存储器单元的更高的密度和可靠性，并消除了野外氧化物的鸟嘴的缺点。

公开(公告)号：US5716874A

公开(公告)日：1998-02-10

申请号：US603248

申请日：1996-02-20

申请人： Joe Ko ,  Gary Hong ,  Chih-Hung Lin

发明人： Joe Ko ,  Gary Hong ,  Chih-Hung Lin

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method of fabricating an EPROM memory increases a coupling ratio and reduces lateral diffusion by forming a gate oxide layer and a coupling insulator individually. A substrate is provided with a field oxide layer to isolate a predetermined active area. A gate oxide layer is formed on the substrate. On the field oxide layer and the gate oxide layer, a polysilicon layer is deposited and defined, whereby a portion of this polysilicon layer and gate oxide layer form a gate electrode. Using the gate electrode as a mask, the substrate is implanted with impurities to provide source and drain electrodes. A dielectric layer is formed on polysilicon layer. A contact window (via) is formed in a predetermined area of dielectric layer. An insulator is deposited and defined by etching, on dielectric layer and the contact window. On the insulator and dielectric layer, a metal contact layer is deposited and defined to cover the insulator.

摘要翻译： 制造EPROM存储器的方法通过单独形成栅极氧化物层和耦合绝缘体来增加耦合比并减小横向扩散。 衬底设置有场氧化物层以隔离预定的有效面积。 在衬底上形成栅氧化层。 在场氧化物层和栅极氧化物层上沉积并限定多晶硅层，由此该多晶硅层和栅极氧化物层的一部分形成栅电极。 使用栅电极作为掩模，衬底被注入杂质以提供源极和漏极。 介电层形成在多晶硅层上。 在电介质层的预定区域中形成接触窗（通孔）。 通过在电介质层和接触窗上进行蚀刻来沉积并限定绝缘体。 在绝缘体和电介质层上，沉积和限定金属接触层以覆盖绝缘体。

公开(公告)号：US5703387A

公开(公告)日：1997-12-30

申请号：US316137

申请日：1994-09-30

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8247 ,  H01L27/115 ,  G11C13/00

CPC分类号： H01L27/11556 ,  H01L27/115

摘要： A vertical split gate memory device has a semiconductor substrate with a trench and a floating gate formed on a sidewall of the trench, thus reducing the surface area of each memory cell. The fabrication process for this device allows precise control over the consistency during fabrication because the length of the floating gate is controlled by the depth of a trench etch and the location of the drains and sources are self-aligned by oxide spacers which act as masks during the doping process.

摘要翻译： 垂直分离栅极存储器件具有形成在沟槽的侧壁上的沟槽和浮栅的半导体衬底，从而减小每个存储单元的表面积。 该器件的制造过程允许在制造期间精确地控制一致性，因为浮栅的长度由沟槽蚀刻的深度控制，并且排水和源的位置通过氧化物隔离物自对准，氧化物间隔物用作掩模 掺杂过程。

公开(公告)号：US5661081A

公开(公告)日：1997-08-26

申请号：US316083

申请日：1994-09-30

申请人： Chen-Chiu Hsue ,  Sun-Chieh Chien ,  Anchor Chen ,  Gary Hong

发明人： Chen-Chiu Hsue ,  Sun-Chieh Chien ,  Anchor Chen ,  Gary Hong

IPC分类号： H01L21/603 ,  H01L23/485 ,  H01L21/283

CPC分类号： H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/49171 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/351

摘要： A process for manufacturing bonding pad adapted for use with an aluminum wire that resists stresses that would otherwise peel the pad from the substrate. The pad has a polysilicon layer adhered to an insulating layer on a semiconductor substrate, a overlying refractory metal polycide layer, a second polysilicon layer, a refractory metal layer, and a thick aluminum alloy bonding pad.

摘要翻译： 一种用于制造适于与铝线一起使用的接合焊盘的方法，其抵抗否则将衬垫从衬底上剥离的应力。 焊盘具有粘附到半导体衬底上的绝缘层，上覆难熔金属多晶硅化物层，第二多晶硅层，难熔金属层和厚铝合金焊盘的多晶硅层。

公开(公告)号：US5625213A

公开(公告)日：1997-04-29

申请号：US500104

申请日：1995-07-10

申请人： Gary Hong ,  Chen-Chiu Hsue

发明人： Gary Hong ,  Chen-Chiu Hsue

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L27/11517

摘要： A method for forming, and a resultant structure of, a top floating gate FLASH EEPROM cell are described. There is a first insulating structure over a silicon substrate, whereby the first insulating structure is a gate oxide. A first conductive structure is formed over the first insulating structure, whereby the first conductive structure is a control gate. There is a first insulating layer over the surfaces of the first conductive structure, whereby the first insulating layer is an interpoly dielectric. There is a second conductive structure formed over the first insulating layer and over a portion of the silicon substrate adjacent to the first insulating structure, whereby the second conductive structure is a floating gate. A second insulating layer is formed between the silicon substrate and the second conductive structure, whereby the second insulating layer is a tunnel oxide. Active regions in the silicon substrate, implanted with a conductivity-imparting dopant, are formed under the second insulating layer but are horizontally a distance from the first insulating structure.

摘要翻译： 描述了用于形成顶部浮置栅极FLASH EEPROM单元的方法和结果。 在硅衬底上存在第一绝缘结构，由此第一绝缘结构是栅极氧化物。 在第一绝缘结构上形成第一导电结构，由此第一导电结构是控制栅极。 在第一导电结构的表面上存在第一绝缘层，由此第一绝缘层是互聚电介质。 在第一绝缘层上形成第二导电结构，并且在与硅衬底相邻的第一绝缘结构的一部分之上形成第二导电结构，由此第二导电结构是浮栅。 在硅衬底和第二导电结构之间形成第二绝缘层，由此第二绝缘层是隧道氧化物。 在第二绝缘层的下方形成硅衬底中注入导电性赋予剂的有源区，但与水平方向距离第一绝缘结构。

公开(公告)号：US5616946A

公开(公告)日：1997-04-01

申请号：US597542

申请日：1996-04-25

申请人： Chen-Chung Hsu ,  Gary Hong

发明人： Chen-Chung Hsu ,  Gary Hong

IPC分类号： H01L21/8229 ,  H01L27/102 ,  H01L27/112

CPC分类号： H01L21/8229 ,  H01L27/1021 ,  Y10S257/91 ,  Y10S438/981

摘要： A method for fabricating read only memory, (ROM), devices, has been developed. The programmable cell of this ROM device is comprised of a P/N diode, place in a N+ buried bit line. The diode formation is accomplished using outdiffusion from a P+ polysilicon wordline, that is in direct contact to a specific bit line region.

摘要翻译： 已经开发了用于制造只读存储器（ROM），器件的方法。 该ROM器件的可编程单元由P / N二极管组成，位于N +掩埋位线中。 二极管形成是通过使用来自P +多晶硅字线的外扩散实现的，其与特定位线区域直接接触。

公开(公告)号：US5576232A

公开(公告)日：1996-11-19

申请号：US353673

申请日：1994-12-12

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8247

CPC分类号： H01L27/11517

摘要： A process for fabricating memory cells for split-gate flash memory devices is disclosed to feature self-alignment and therefore precisely defined channel lengths for the floating-gate and isolation transistors of the memory cell. A gate oxide layer, a first conducting layer, and a gate dielectric layer are formed in sequence on a semiconductor substrate. A conducting strip is formed on the gate dielectric layer. The conducting strip is covered with a shielding layer. The gate dielectric layer, the first conducting layer and the gate oxide layer are etched utilizing the shielding layer as a shielding mask to form a control gate for the memory cell. Thermal oxidation is applied to the entire substrate utilizing the shielding layer as a shielding mask to form a tunnel oxide layer on the surface of the substrate and isolating oxide layers on the sidewalls of the control gate. The shielding layer is removed. Electrically conducting sidewall spacers are formed on both of the sidewalls of the conducting strip. Each of the conducting sidewall spacers cover a portion of the tunnel oxide layer and are also electrically isolated from the control gate by the isolating oxide layer, forming the floating gate for the memory cell. Impurities are implanted utilizing the conducting strip and the conducting sidewall spacers as shielding masks to form source and drain regions on the substrate for the memory cell.

摘要翻译： 公开了用于制造用于分离栅极闪存器件的存储器单元的工艺，其特征在于自对准，因此具有针对存储器单元的浮置栅极和隔离晶体管的精确限定的沟道长度。 在半导体衬底上依次形成栅极氧化物层，第一导电层和栅极电介质层。 导电条形成在栅介质层上。 导电带被屏蔽层覆盖。 使用屏蔽层作为屏蔽掩模蚀刻栅极介电层，第一导电层和栅极氧化物层，以形成用于存储单元的控制栅极。 使用屏蔽层作为屏蔽掩模，将热氧化施加到整个基板上，以在基板的表面上形成隧道氧化物层，并隔离控制栅极的侧壁上的氧化物层。 屏蔽层被去除。 在导电条的两个侧壁上形成导电侧壁间隔物。 每个导电侧壁间隔物覆盖隧道氧化物层的一部分，并且还通过隔离氧化物层与控制栅极电隔离，形成用于存储单元的浮动栅极。 使用导电条和导电侧壁间隔物作为屏蔽掩模注入杂质，以在存储器单元的衬底上形成源区和漏区。

公开(公告)号：US5571739A

公开(公告)日：1996-11-05

申请号：US497883

申请日：1995-07-03

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8246

CPC分类号： H01L27/11246 ,  Y10S438/981

摘要： A method of manufacturing an improved Read-Only-Memory (ROM) device, was achieved. The array of programmed ROM cells composed of field effect transistors (FETs) are fabricated having improved bit lines with lower resistance. The method utilizes the selective deposition of silicon oxide by a method of Liquid Phase Deposition (LPD) to form a thick insulating oxide layer over the gate oxide of the FET in the coded memory cells. The thick insulating oxide raises the threshold voltage of the FET, preventing the FET from turning on when a gate voltage is applied. The coding using a thick insulating oxide eliminates the need to code the ROM memory cells by ion implantation, and thereby prevents the counter-doping of the bit lines which results in the high bit line resistivity that degrades circuit performance.

摘要翻译： 实现了改进的只读存储器（ROM）器件的制造方法。 由场效应晶体管（FET）构成的编程ROM单元的阵列被制造成具有更低电阻的改进的位线。 该方法利用液相沉积（LPD）的方法选择性沉积氧化硅，以在编码存储单元中的FET的栅极氧化物上形成厚的绝缘氧化物层。 厚的绝缘氧化物提高FET的阈值电压，防止当施加栅极电压时FET导通。 使用厚绝缘氧化物的编码消除了通过离子注入对ROM存储单元进行编码的需要，从而防止导致高位线电阻率的位线的反掺杂降低了电路性能。

公开(公告)号：US5550075A

公开(公告)日：1996-08-27

申请号：US374967

申请日：1995-01-19

申请人： Chen-Chung Hsu ,  Gary Hong

发明人： Chen-Chung Hsu ,  Gary Hong

IPC分类号： H01L21/8229 ,  H01L27/102 ,  H01L21/265

CPC分类号： H01L21/8229 ,  H01L27/1021 ,  Y10S257/91 ,  Y10S438/981

摘要： A method for fabricating read only memory, (ROM), devices, has been developed. The programmable cell of this ROM device is comprised of a P/N diode, place in a N+ buried bit line. The diode formation is accomplished using outdiffusion from a P+ polysilicon wordline, that is in direct contact to a specific bit line region.

摘要翻译： 已经开发了用于制造只读存储器（ROM），器件的方法。 该ROM器件的可编程单元由P / N二极管组成，位于N +掩埋位线中。 二极管形成是通过使用来自P +多晶硅字线的外扩散实现的，其与特定位线区域直接接触。

公开(公告)号：US5536673A

公开(公告)日：1996-07-16

申请号：US507536

申请日：1995-07-26

申请人： Gary Hong ,  Jason Jyh-shyang Jenq

发明人： Gary Hong ,  Jason Jyh-shyang Jenq

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method is desired for making an array of dynamic random access memory (DRAM) cells having stacked capacitors with increased capacitance. The method involves forming a bottom electrode having a lower and upper fin-shaped portion in which a vertical extension is formed on the lower fin-shape portion at the same time that the upper fin is formed. This increases the capacitance of the stacked capacitor. The bottom electrode is formed by patterning a thick expendable silicon oxide layer and an underlying doped polysilicon layer (lower fin portion). Another polysilicon layer (upper fin portion is conformally coated over the thick insulating layer and patterned with an etch mask, which is smaller than the patterned insulating layer. An anisotropic etch is performed that forms the upper fin portion, the vertical extension on the lower fin portion and electrically isolates the array of electrodes. The capacitors are then completed by removing the expendable oxide layer, forming a capacitor dielectric layer on the bottom electrode, and patterning a doped polysilicon layer for the top electrode of the stacked capacitor.

摘要翻译： 期望制造具有增加的电容的堆叠电容器的动态随机存取存储器（DRAM）单元阵列的方法。 该方法包括在形成上翅片的同时形成具有下翅片形状部分和上鳍形部分的底部电极，其中在下翅片形部分上形成垂直延伸部。 这增加了堆叠电容器的电容。 底部电极通过图案化厚的消耗性氧化硅层和下面的掺杂多晶硅层（下部翅片部分）来形成。 另一个多晶硅层（上鳍部分被保形地涂覆在厚的绝缘层上，并用蚀刻掩模图案化，该蚀刻掩模小于图案化的绝缘层），进行各向异性蚀刻，形成上鳍部分，下翅片上的垂直延伸部 部分并电隔离电极阵列，然后通过去除消耗性氧化物层，在底部电极上形成电容器电介质层，并对叠层电容器的顶部电极的掺杂多晶硅层进行构图来完成电容器。