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    Method of forming a DRAM stacked capacitor cell
    2.
    发明授权
    Method of forming a DRAM stacked capacitor cell 失效
    形成DRAM叠层电容器单元的方法

    公开(公告)号：US5413950A

    公开(公告)日：1995-05-09

    申请号：US231461

    申请日：1994-04-22

    申请人： Anchor Chen ,  Min-Tzong Yang ,  Chen-Chiu Hsue ,  Gary Hong

    发明人： Anchor Chen ,  Min-Tzong Yang ,  Chen-Chiu Hsue ,  Gary Hong

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/00 ,  H01L21/70

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82

    摘要： A new stacked capacitor structure having increased capacitance and a method of fabrication was accomplished. The capacitor stores data in the form of stored charge and together with a field effect transistor (MOSFET) make up the individual Dynamic Random Access Memory (DRAM) storage cells on a DRAM chip. The improved capacitor is fabricated using an electrically conducting layer in the bottom electrode of the capacitor, which is substantially different in composition from silicon. The conducting layer preferably being a refractory metal or a refactory metal silicides, such as, tungsten (W) or tungsten silicide (WSi). The bottom electrode is formed from a multilayer composed of a thin polysilicon layer, the conducting layer and an upper thicker polysilicon layer. Vertical capacitor sidewalls are formed from the upper polysilicon layer by photoresist masking and then etching to the conducting layer. The conducting layer provides an etch end point for accurately etching to the correct depth without over etching. This provides a repeatable and more manufacturable process. The stacked capacitor is then completed by depositing a high dielectric constant insulator layer over the bottom electrode and then forming the top capacitor electrode, thereby completing the stacked capacitor.

    摘要翻译： 实现了具有增加的电容的新的堆叠电容器结构和制造方法。 电容器以存储电荷的形式存储数据，并与场效应晶体管（MOSFET）一起组成DRAM芯片上的单独的动态随机存取存储器（DRAM）存储单元。 改进的电容器使用电容器的底部电极中的导电层制造，其与硅的组成基本上不同。 导电层优选为难熔金属或重构金属硅化物，例如钨（W）或硅化钨（WSi）。 底部电极由由多晶硅薄层，导电层和较厚的多晶硅层构成的多层构成。 垂直电容器侧壁由上多晶硅层通过光刻胶掩模形成，然后蚀刻到导电层。 导电层提供蚀刻终点，用于在没有过蚀刻的情况下精确地蚀刻到正确的深度。 这提供了可重复和更可制造的过程。 然后通过在底部电极上沉​​积高介电常数绝缘体层然后形成顶部电容器电极来完成叠层电容器，由此完成叠层电容器。

    Top floating-gate flash EEPROM structure
    3.
    发明授权
    Top floating-gate flash EEPROM structure 失效
    顶部浮栅闪存EEPROM结构

    公开(公告)号：US5625213A

    公开(公告)日：1997-04-29

    申请号：US500104

    申请日：1995-07-10

    申请人： Gary Hong ,  Chen-Chiu Hsue

    发明人： Gary Hong ,  Chen-Chiu Hsue

    IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L29/788

    CPC分类号： H01L29/66825 ,  H01L27/11517

    摘要： A method for forming, and a resultant structure of, a top floating gate FLASH EEPROM cell are described. There is a first insulating structure over a silicon substrate, whereby the first insulating structure is a gate oxide. A first conductive structure is formed over the first insulating structure, whereby the first conductive structure is a control gate. There is a first insulating layer over the surfaces of the first conductive structure, whereby the first insulating layer is an interpoly dielectric. There is a second conductive structure formed over the first insulating layer and over a portion of the silicon substrate adjacent to the first insulating structure, whereby the second conductive structure is a floating gate. A second insulating layer is formed between the silicon substrate and the second conductive structure, whereby the second insulating layer is a tunnel oxide. Active regions in the silicon substrate, implanted with a conductivity-imparting dopant, are formed under the second insulating layer but are horizontally a distance from the first insulating structure.

    摘要翻译： 描述了用于形成顶部浮置栅极FLASH EEPROM单元的方法和结果。 在硅衬底上存在第一绝缘结构，由此第一绝缘结构是栅极氧化物。 在第一绝缘结构上形成第一导电结构，由此第一导电结构是控制栅极。 在第一导电结构的表面上存在第一绝缘层，由此第一绝缘层是互聚电介质。 在第一绝缘层上形成第二导电结构，并且在与硅衬底相邻的第一绝缘结构的一部分之上形成第二导电结构，由此第二导电结构是浮栅。 在硅衬底和第二导电结构之间形成第二绝缘层，由此第二绝缘层是隧道氧化物。 在第二绝缘层的下方形成硅衬底中注入导电性赋予剂的有源区，但与水平方向距离第一绝缘结构。

    Process for making a mask ROM with self-aligned coding technology
    4.
    发明授权
    Process for making a mask ROM with self-aligned coding technology 失效
    用自制编码技术制作掩模ROM的过程

    公开(公告)号：US5472898A

    公开(公告)日：1995-12-05

    申请号：US287949

    申请日：1994-08-09

    申请人： Gary Hong ,  Chen-Chiu Hsue

    发明人： Gary Hong ,  Chen-Chiu Hsue

    IPC分类号： H01L21/8246 ,  H01L21/265

    CPC分类号： H01L27/1126

    摘要： A self-aligned coding process for mask ROM is disclosed. First, a substrate having a plurality of bit-lines formed therein, a gate oxide layer formed on the bit-lines, and a plurality of word-lines formed on the gate oxide, which together construct an array of memory cells, is provided. Next, a barrier layer is formed on the word-lines. A silicon dioxide layer is formed on the gate oxide between the word-lines by using liquid phase deposition, wherein the thickness of the silicon dioxide layer is larger than that of the word-lines. Then, the barrier layer is removed. A mask layer is formed on the substrate exposing parts of the memory cells that will be programmed. Finally, impurities are implanted into the substrate not covered by the mask layer and the silicon dioxide layer to make the memory cells that will be programmed operating in a first state, and leave other non-programmed memory cells operating in a second state.

    摘要翻译： 公开了一种用于掩模ROM的自对准编码处理。 首先，提供一种形成在其中的多个位线的衬底，形成在位线上的栅极氧化层，以及形成在栅极氧化物上的多个字线，这些字线一起构成存储单元阵列。 接下来，在字线上形成阻挡层。 通过使用液相沉积在字线之间的栅极氧化物上形成二氧化硅层，其中二氧化硅层的厚度大于字线的厚度。 然后，去除阻挡层。 在衬底上形成露出将被编程的存储器单元的部分的掩模层。 最后，将杂质注入到未被掩模层和二氧化硅层覆盖的衬底中，以使将被编程的存储器单元在第一状态下工作，并使其它非编程存储器单元在第二状态下工作。

    Process on thickness control for silicon-on-insulator technology
    5.
    发明授权
    Process on thickness control for silicon-on-insulator technology 失效
    绝缘体上硅技术的厚度控制工艺

    公开(公告)号：US5449638A

    公开(公告)日：1995-09-12

    申请号：US254532

    申请日：1994-06-06

    申请人： Gary Hong ,  Chen-Chiu Hsue ,  H. J. Wu ,  Lawrence Y. Lin

    发明人： Gary Hong ,  Chen-Chiu Hsue ,  H. J. Wu ,  Lawrence Y. Lin

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76251 ,  Y10S148/012 ,  Y10S148/135

    摘要： A method for forming a thin, uniform top silicon layer using bonded-wafer SOI technology is described. A dielectric layer is formed on a first surface of a first silicon substrate. A trench is formed in a first surface of a second silicon substrate. A polishing stopper is formed in the trench. A second dielectric layer with a smooth top surface is formed over the polishing stopper and over the first surface of the second silicon substrate. The smooth top surface of the second dielectric layer of the second silicon substrate is bonded to the dielectric layer of the first silicon substrate. Material is removed from the exposed surface of the second silicon substrate to form the silicon layer with well-controlled thickness, having a top surface co-planar with the polishing stopper.

    摘要翻译： 描述了使用接合晶片SOI技术形成薄的均匀顶部硅层的方法。 介电层形成在第一硅衬底的第一表面上。 在第二硅衬底的第一表面中形成沟槽。 在沟槽中形成抛光止动件。 在抛光止动器上方并在第二硅衬底的第一表面上形成具有平滑顶表面的第二电介质层。 第二硅衬底的第二电介质层的平滑顶表面结合到第一硅衬底的电介质层。 从第二硅衬底的暴露表面去除材料以形成具有良好控制厚度的硅层，其具有与抛光止挡件共面的顶表面。

    Method of forming bit lines having lower conductivity in their respective edges
    6.
    发明授权
    Method of forming bit lines having lower conductivity in their respective edges 失效
    在各自的边缘形成具有较低导电性的位线的方法

    公开(公告)号：US5672532A

    公开(公告)日：1997-09-30

    申请号：US242787

    申请日：1994-05-16

    申请人： Chen Chiu Hsue ,  Gary Hong

    发明人： Chen Chiu Hsue ,  Gary Hong

    IPC分类号： H01L21/8246 ,  H01L21/265

    CPC分类号： H01L27/1126 ,  Y10S438/965

    摘要： A buried bit line ROM is disclosed having orthogonal sets of buried bit lines and polysilicon word lines. Polysilicon spacers are disposed on either side of each of the bit lines. The polysilicon spacers are slightly doped. The bit lines have a doping profile so that the edges of each bit line is doped less and the center of each bit line is doped more.

    摘要翻译： 公开了一种掩埋位线ROM，其具有正交集合的掩埋位线和多晶硅字线。 多晶硅间隔物设置在每个位线的任一侧上。 多晶硅间隔物稍微掺杂。 位线具有掺杂分布，使得每个位线的边缘被掺杂较少，并且每个位线的中心被更多地掺杂。

    High coupling ratio of flash memory
    7.
    发明授权
    High coupling ratio of flash memory 失效
    闪存的高耦合比

    公开(公告)号：US5585656A

    公开(公告)日：1996-12-17

    申请号：US435190

    申请日：1995-05-05

    申请人： Chen-Chiu Hsue ,  Gary Hong

    发明人： Chen-Chiu Hsue ,  Gary Hong

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788

    CPC分类号： H01L29/66825 ,  H01L21/28141

    摘要： A new method of fabricating a high coupling ratio Flash EEPROM memory cell is achieved. A layer of silicon dioxide is provided over the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon dioxide layer and patterned. The silicon dioxide layer not covered by the patterned silicon nitride layer is removed, thereby exposing portions of the substrate. A tunnel oxide layer is grown on the exposed portions of the semiconductor substrate. Silicon nitride spacers are formed on the sidewalls of the patterned silicon nitride layer. Ions are implanted into the substrate using the silicon nitride layer and spacers as a mask to form implanted regions within the semiconductor substrate. The semiconductor substrate is oxidized where the implanted regions have been formed leaving the thin tunnel oxide only under the silicon nitride spacers. The silicon nitride layer and spacers are removed. A first polysilicon layer is deposited over the surface of the silicon dioxide and tunnel oxide layers and patterned to form a floating gate. An interpoly dielectric layer is deposited over the patterned first polysilicon layer followed by a second polysilicon layer. The second polysilicon layer is patterned to form a control gate. Passivation and metallization complete the fabrication of the memory cell with improved coupling ratio.

    摘要翻译： 实现了一种制造高耦合比闪存EEPROM存储单元的新方法。 在半导体衬底的表面上设置一层二氧化硅。 一层氮化硅沉积在二氧化硅层上并构图。 未被图案化氮化硅层覆盖的二氧化硅层被去除，从而暴露衬底的部分。 在半导体衬底的暴露部分上生长隧道氧化物层。 在图案化氮化硅层的侧壁上形成氮化硅间隔物。 使用氮化硅层和间隔物作为掩模将离子注入到衬底中，以在半导体衬底内形成注入区域。 半导体衬底被氧化，其中已经形成注入区域，仅在氮化硅间隔物之下留下薄的隧道氧化物。 去除氮化硅层和间隔物。 第一多晶硅层沉积在二氧化硅和隧道氧化物层的表面上并被图案化以形成浮栅。 在图案化的第一多晶硅层之后沉积多层介电层，随后是第二多晶硅层。 图案化第二多晶硅层以形成控制栅极。 钝化和金属化完成了具有改进的耦合比的存储器单元的制造。

    ROM coding process with self-aligned implantation and the ROM produced thereby
    8.
    发明授权
    ROM coding process with self-aligned implantation and the ROM produced thereby 失效
    具有自对准植入的ROM编码处理和由此产生的ROM

    公开(公告)号：US5576235A

    公开(公告)日：1996-11-19

    申请号：US342630

    申请日：1994-11-21

    申请人： Gary Hong ,  Chen-Chiu Hsue ,  Chen-Hui Chung

    发明人： Gary Hong ,  Chen-Chiu Hsue ,  Chen-Hui Chung

    IPC分类号： H01L21/8246 ,  H01L27/112

    CPC分类号： H01L27/1126 ,  H01L27/112

    摘要： A ROM coding method with self-aligned implantation. First, a non-coded mask ROM with a silicon substrate, a plurality of bit-lines formed in the substrate, a gate oxide layer formed on the bit-lines, and a plurality of word-lines formed on the gate oxide, which together form arrays of memory cells, is provided. Next, an aligning layer is formed above the word-lines. A photoresist is thereafter coated on the surface of the aligning layer. Then, portions of the photoresist not covered by a mask pattern are etched away to the aligning layer so as to provide openings exposing portions of the memory cells that will be programmed to operate in a first conduction state. Portions of the aligning layer exposed through the openings are then removed, after which impurities are implanted through the openings and into the substrate to enable the memory cells that are to operate in the first conduction state, and leave other non-programmed memory cells operating in a second conduction state.

    摘要翻译： 具有自对准植入的ROM编码方法。 首先，具有硅衬底的非编码掩模ROM，在衬底中形成的多个位线，形成在位线上的栅极氧化层，以及形成在栅极氧化物上的多个字线，其一起 提供了存储单元的阵列。 接下来，在字线上形成对准层。 然后将光致抗蚀剂涂覆在对准层的表面上。 然后，未被掩模图案覆盖的部分光致抗蚀剂被蚀刻掉到对准层上，以便提供露出将被编程为在第一导通状态下操作的存储单元部分的开口。 然后去除通过开口暴露的对准层的部分，之后通过开口注入杂质并进入衬底，以使得能够在第一导通状态下操作的存储器单元，并且使其他非编程存储器单元在 第二导通状态。

    Self-aligned coding process for mask ROM
    9.
    发明授权
    Self-aligned coding process for mask ROM 失效
    掩模ROM的自对准编码过程

    公开(公告)号：US5529942A

    公开(公告)日：1996-06-25

    申请号：US264738

    申请日：1994-06-23

    申请人： Gary Hong ,  Chen-Chiu Hsue

    发明人： Gary Hong ,  Chen-Chiu Hsue

    IPC分类号： H01L21/8246 ,  H01L21/266

    CPC分类号： H01L27/1126

    摘要： A ROM coding method with a self-aligned implantation. First, a non-coded mask ROM with a semiconductor substrate, a plurality of bit-lines formed on the semiconductor substrate, a gate oxide formed over the semiconductor substrate and the bit-line, and a plurality of word-lines formed above the gate oxide, which together form memory cells, is provided. Before the word-lines are formed, a barrier material is applied over spacing strips between the locations where the word-lines are to be formed. The barrier material serves as a mask through which impurities are implanted into the substrate to selectively program the memory cells to operate in either a first or second conduction state.

    摘要翻译： 具有自对准植入的ROM编码方法。 首先，具有半导体衬底的非编码掩模ROM，形成在半导体衬底上的多个位线，形成在半导体衬底上的栅极氧化物和位线，以及形成在栅极上方的多个字线 一起形成记忆单元的氧化物。 在形成字线之前，在要形成字线的位置之间的间隔条上施加阻挡材料。 阻挡材料用作掩模，通过该掩模将杂质注入到衬底中以选择性地对存储器单元进行编程以在第一或第二导通状态下工作。

    Buried bit line DRAM cell
    10.
    发明授权
    Buried bit line DRAM cell 失效
    埋地位线DRAM单元

    公开(公告)号：US5468980A

    公开(公告)日：1995-11-21

    申请号：US334046

    申请日：1994-11-04

    申请人： Ming-Tzong Yang ,  Chen-Chiu Hsue ,  Gary Hong

    发明人： Ming-Tzong Yang ,  Chen-Chiu Hsue ,  Gary Hong

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： Ions of dopant are implanted into predetermined locations in a doped semiconductor substrate in sufficient concentration to form a buried conductor regions. A thick dielectriv layer overlies the surface of the doped substrate. A first polysilicon layer is formed and patterned on the silicon dioxide layer by a mask and etching to form conductor lines, covered by a dielectric. A second polysilicon layer is formed on the second dielectric layer and patterned to form a first capacitor plate. A third dielectric layer is formed on the surface of the second polysilicon layer. A third polysilicon layer is formed on the third dielectric layer and patterned to form a top capacitor plate. A layer of BPSG is deposited upon the third layer of polysilicon.

    摘要翻译： 掺杂剂的离子以足够的浓度注入掺杂半导体衬底中的预定位置以形成掩埋导体区域。 厚的介电层覆盖在掺杂衬底的表面上。 通过掩模和蚀刻在二氧化硅层上形成并图案化第一多晶硅层以形成由电介质覆盖的导体线。 在第二电介质层上形成第二多晶硅层并构图以形成第一电容器板。 在第二多晶硅层的表面上形成第三电介质层。 在第三电介质层上形成第三多晶硅层并构图以形成顶部电容器板。 一层BPSG沉积在第三层多晶硅上。