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公开(公告)号：US20210057631A1
公开(公告)日：2021-02-25
申请号：US16996595
申请日：2020-08-18
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , George E.G. Sterling , Christopher B. Rich
Abstract: Addressing a superconducting flux storage device may include applying a bias current, a low-frequency flux bias, and a high-frequency flux bias in combination to cause a combined address signal level to exceed a defined address signal latching level for the superconducting flux storage device. A bias current that, in combination with a low-frequency flux bias and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ. A low-frequency flux bias that, in combination with a bias current and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ.
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公开(公告)号：US20200266234A1
公开(公告)日：2020-08-20
申请号：US16389669
申请日：2019-04-19
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T.R. Boothby , Loren J. Swenson , Mark H. Volkmann , Jed D. Whittaker
Abstract: Apparatus and methods advantageously provide parallel-plate capacitors in superconducting integrated circuits. A method may include forming a metal-oxide layer to overlie at least a portion of a first capacitor plate, the first capacitor plate comprising a superconductive material, and depositing a second capacitor plate to overlie at least a portion of the metal-oxide layer, the second capacitor plate comprising a superconductive material. The method may include depositing a base electrode of superconductive material to overlie at least a portion of a substrate, depositing the first capacitor plate to overlie at least a portion of the base electrode, and superconductingly electrically coupled to the base electrode, and depositing a counter electrode of superconductive material to overlie at least a portion of the second capacitor plate, the counter electrode superconductingly electrically coupled to the second capacitor plate. The superconducting integrated circuit may include a parallel-plate capacitor and a Josephson junction.
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公开(公告)号：US20190089031A1
公开(公告)日：2019-03-21
申请号：US16134592
申请日：2018-09-18
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexandr M. Tcaciuc , Loren J. Swenson , George E.G. Sterling
Abstract: Adaptions and improvements to coaxial metal powder filters include distributing a dissipative matrix mixture comprising superconductive material, metal powder, epoxy, and/or magnetic material within a volume defined by an outer tubular conductor and inner conductor. The frequency response of the filter may be tuned by exploiting the energy gap frequency of superconductive material in the dissipative matrix. The inner surface of the outer tubular conductor may be covered with a superconductive material. For a dissipative matrix comprising magnetic material or superconductive powder particles of a certain size, an external magnetic field can be applied to tune the frequency response of the filter.
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公开(公告)号：US20170178018A1
公开(公告)日：2017-06-22
申请号：US15382278
申请日：2016-12-16
Applicant: D-Wave Systems Inc.
Inventor： Alexandr M. Tcaciuc , Pedro A. de Buen , Peter D. Spear , Sergey V. Uchaykin , Colin C. Enderud , Richard D. Neufeld , Jeremy P. Hilton , J. Craig Petroff , Amar B. Kamdar , Gregory D. Peregrym , Edmond Ho Yin Kan , Loren J. Swenson , George E.G. Sterling , Gregory Citver
IPC: G06N99/00 , H01L39/12 , H01L39/24 , H05K3/34 , H05K9/00 , F25B43/00 , H01L39/18 , H01F41/06 , H01F41/04 , H01F13/00 , F25B9/12 , H03H3/00 , H05K1/02
CPC classification number: G06N10/00 , H01F13/006 , H01F41/048 , H01F41/076 , H01L39/02 , H01L39/14 , H03H3/00 , H03H7/425 , H03H2001/005 , H05K1/0233 , H05K1/0245 , H05K1/16 , H05K2201/10287
Abstract: An electrical filter includes a dielectric substrate with inner and outer coils about a first region and inner and outer coils about a second region, a portion of cladding removed from wires that form the coils and coupled to electrically conductive traces on the dielectric substrate via a solder joint in a switching region. An apparatus to thermally couple a superconductive device to a metal carrier with a through-hole includes a first clamp and a vacuum pump. A composite magnetic shield for use at superconductive temperatures includes an inner layer with magnetic permeability of at least 50,000; and an outer layer with magnetic saturation field greater than 1.2 T, separated from the inner layer by an intermediate layer of dielectric. An apparatus to dissipate heat from a superconducting processor includes a metal carrier with a recess, a post that extends upwards from a base of the recess and a layer of adhesive on top of the post. Various cryogenic refrigeration systems are described.
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公开(公告)号：US12248849B2
公开(公告)日：2025-03-11
申请号：US18444208
申请日：2024-02-16
Applicant: D-WAVE SYSTEMS INC.
Inventor： Steven P. Reinhardt , Andrew D. King , Loren J. Swenson , Warren T. E. Wilkinson , Trevor Michael Lanting
IPC: G06N10/00 , G05B19/042
Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
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Patent Agency Ranking
公开(公告)号：US20250040454A1
公开(公告)日：2025-01-30
申请号：US18790374
申请日：2024-07-31
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , George E.G. Sterling , Mark H. Volkmann , Colin C. Enderud
Abstract: A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.
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公开(公告)号：US20250038722A1
公开(公告)日：2025-01-30
申请号：US18716679
申请日：2022-12-06
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , Jed D. Whittaker , George E.G. Sterling
Abstract: In an implementation, a tunable traveling wave parametric amplifier (TWPA) includes a T-stage that includes a first DC-SQUID and a first interface inductively communicatively coupled to the first DC SQUID operable to apply a first bias to the first DC SQUID. The T-stage also includes a second DC-SQUID electrically communicatively coupled to the first DC-SQUID in series via a center node, and a second interface inductively communicatively coupled to the second DC-SQUID operable to apply a second bias to the second DC-SQUID. The TWPA also includes a shunting resonator communicatively coupled to the center node via a coupling capacitance. The shunting resonator includes a third DC-SQUID, and a third interface inductively communicatively coupled to the third DC SQUID operable to apply a third bias to the third DC SQUID. The first, second, and third biases are adjustable to improve a bandwidth of the tunable TWPA.
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公开(公告)号：US20250013900A1
公开(公告)日：2025-01-09
申请号：US18444208
申请日：2024-02-16
Applicant: D-WAVE SYSTEMS INC.
Inventor： Steven P. Reinhardt , Andrew D. King , Loren J. Swenson , Warren T.E. Wilkinson , Trevor Michael Lanting
IPC: G06N10/00 , G05B19/042
Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
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公开(公告)号：US11957065B2
公开(公告)日：2024-04-09
申请号：US17321819
申请日：2021-05-17
Applicant: D-WAVE SYSTEMS INC.
Inventor： Shuiyuan Huang , Byong H. Oh , Douglas P. Stadtler , Edward G. Sterpka , Paul I. Bunyk , Jed D. Whittaker , Fabio Altomare , Richard G. Harris , Colin C. Enderud , Loren J. Swenson , Nicolas C. Ladizinsky , Jason J. Yao , Eric G. Ladizinsky
IPC: H10N60/01 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H10N60/85 , H10N69/00
CPC classification number: H10N60/0156 , H01L21/76891 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L23/53257 , H01L23/53285 , H10N60/85 , H10N69/00
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.
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公开(公告)号：US11874344B2
公开(公告)日：2024-01-16
申请号：US18082385
申请日：2022-12-15
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , Andrew J. Berkley , Mark H. Volkmann , George E. G. Sterling , Jed D. Whittaker
IPC: G01R33/035 , G06N10/00 , H10N60/12
CPC classification number: G01R33/0354 , G06N10/00 , H10N60/12
Abstract: A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
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