公开(公告)号：US09406767B1

公开(公告)日：2016-08-02

申请号：US15073050

申请日：2016-03-17

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Sanjay C. Mehta ,  Balasubramanian S. Pranatharthiharan ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/4983 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76205 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42368 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.

Abstract translation: 在栅极之间填充沟槽的方法包括在衬底上形成第一和第二虚拟栅极，第一和第二伪栅极包括牺牲栅极材料和硬掩模层; 沿着第一伪栅极的侧壁形成第一栅极间隔物，沿着第二虚拟栅极的侧壁形成第二栅极间隔物; 执行外延生长工艺以在第一和第二虚拟栅极之间的衬底上形成源极/漏极; 在第一和第二伪栅极和源极/漏极上设置保形衬垫; 在第一和第二伪栅极之间的保形衬垫上设置氧化物; 将氧化物凹陷到低于第一和第二伪栅极的硬掩模层的水平以形成凹陷氧化物; 以及在第一伪栅极和第二虚拟栅极之间的凹陷氧化物上沉积间隔物材料。

公开(公告)号：US10790148B2

公开(公告)日：2020-09-29

申请号：US15987018

申请日：2018-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Heimanu Niebojewski ,  Ruilong Xie ,  Andrew M. Greene

IPC: H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device includes forming a composite spacer architecture over sidewalls of a sacrificial gate disposed over a semiconductor layer, and the subsequent deposition of a supplemental sacrificial gate over the sacrificial gate. A recess etch of the composite spacer architecture is followed by the formation within the recess of a sacrificial capping layer. The supplemental sacrificial gate and the sacrificial gate are removed to expose the composite spacer architecture, which is selectively etched to form a T-shaped cavity overlying a channel region of the semiconductor layer. A replacement metal gate is formed within a lower region of the T-shaped cavity, and a self-aligned contact (SAC) capping layer is formed within an upper region of the T-shaped cavity prior to metallization of the device.

公开(公告)号：US20190252268A1

公开(公告)日：2019-08-15

申请号：US15897204

申请日：2018-02-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Laertis Economikos ,  Andrew M. Greene ,  Siva Kanakasabapathy ,  John R. Sporre

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L21/823864 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545

Abstract: Gate isolation methods and structures leverage the formation of a sidewall spacer layer within a recess formed in an organic planarization layer. The spacer layer enables precise alignment of the cut region of a sacrificial gate, which may be backfilled with an isolation layer. By forming the isolation layer after a reliability anneal of the gate dielectric and after formation of a first work function metal layer, both the desired critical dimension (CD) and alignment of the isolation layer can be achieved.

公开(公告)号：US09923078B2

公开(公告)日：2018-03-20

申请号：US14928719

申请日：2015-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/283 ,  H01L27/088 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L29/665 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

公开(公告)号：US20170287776A1

公开(公告)日：2017-10-05

申请号：US15625360

申请日：2017-06-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/311 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

公开(公告)号：US20170178967A1

公开(公告)日：2017-06-22

申请号：US15359953

申请日：2016-11-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Andrew M. Greene ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L27/088

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

公开(公告)号：US09659786B2

公开(公告)日：2017-05-23

申请号：US14799297

申请日：2015-07-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Andrew M. Greene ,  Ryan O. Jung ,  Ruilong Xie

IPC: H01L21/336 ,  H01L21/311 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L21/283 ,  H01L21/0332 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/0207 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553

Abstract: A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.

公开(公告)号：US20170076987A1

公开(公告)日：2017-03-16

申请号：US15342801

申请日：2016-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

Abstract translation: 用于填充结构之间的间隙的方法包括通过间隙形成彼此相邻的多个高纵横比结构，在结构的顶部上形成第一介电层，并在结构上共形沉积间隔电介质层。 间隔电介质层从水平表面去除，保护层共形沉积在结构上。 间隙填充有可流动电介质，其通过选择性蚀刻工艺凹陷到结构侧壁的高度，使得保护层保护结构侧壁上的间隔电介质层。 使用比保护层更高的蚀刻电阻将第一介电层和间隔电介质层暴露在高度之上，以通过蚀刻工艺保持间隔层电介质的尺寸。 间隙由高密度等离子体填充物填充。

公开(公告)号：US20170018628A1

公开(公告)日：2017-01-19

申请号：US15156651

申请日：2016-05-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Andrew M. Greene ,  Ryan O. Jung ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/308 ,  H01L29/40

CPC classification number: H01L21/283 ,  H01L21/0332 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/0207 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553

Abstract: A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.

公开(公告)号：US20170018437A1

公开(公告)日：2017-01-19

申请号：US14799297

申请日：2015-07-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Andrew M. Greene ,  Ryan O. Jung ,  Ruilong Xie

IPC: H01L21/311 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L21/283 ,  H01L21/0332 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/0207 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553

Abstract: A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.

Abstract translation: 用于在栅极切割区域中保留层间电介质的方法包括使介电填充物凹陷以暴露在器件区域和切割区域中形成的栅极结构的盖层，并且在凹入的介电填充物顶部的凹部中形成衬垫。 衬垫包括提供蚀刻选择性以保护电介质填料的材料。 切割区域中的栅极结构被凹入以使用衬垫形成栅极凹部，以保护电介质填充物免受蚀刻。 使用衬垫从栅极结构中去除栅极材料以保护电介质填充物免受蚀刻。 形成介质间隙填充物以取代栅极材料并填充切割区域中的栅极凹槽。