公开(公告)号：US10699942B2

公开(公告)日：2020-06-30

申请号：US15961337

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/78

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

公开(公告)号：US20200066899A1

公开(公告)日：2020-02-27

申请号：US16664056

申请日：2019-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

Abstract: A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.

公开(公告)号：US10535771B1

公开(公告)日：2020-01-14

申请号：US16016828

申请日：2018-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L21/02

Abstract: A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.

公开(公告)号：US10522538B1

公开(公告)日：2019-12-31

申请号：US16032108

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Shesh Mani Pandey ,  Jiehui Shu ,  Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Guowei Xu ,  Zhaoying Hu

IPC: H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.

公开(公告)号：US20190393335A1

公开(公告)日：2019-12-26

申请号：US16016828

申请日：2018-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

Abstract: A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.

公开(公告)号：US20190273148A1

公开(公告)日：2019-09-05

申请号：US16415519

申请日：2019-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/417

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US10355104B2

公开(公告)日：2019-07-16

申请号：US15795833

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Sang Woo Lim ,  Kyung-Bum Koo ,  Alina Vinslava ,  Pei Zhao ,  Zhenyu Hu ,  Hsien-Ching Lo ,  Joseph F. Shepard, Jr. ,  Shesh Mani Pandey

IPC: H01L21/02 ,  H01L21/84 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

公开(公告)号：US10083904B2

公开(公告)日：2018-09-25

申请号：US14993238

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Shesh Mani Pandey

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L21/321 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/02167 ,  H01L21/02271 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295

Abstract: Methodologies and a device for reducing capacitance and improving profile control are provided. Embodiments include forming metal vias in a first dielectric layer; forming a graded interlayer dielectric over the metal vias; forming a metal layer in the graded ILD over one of the metal vias; and forming a hydrogenated amorphous silicon carbon film over the metal layer.

公开(公告)号：US10079308B1

公开(公告)日：2018-09-18

申请号：US15682631

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shesh Mani Pandey ,  Hui Zang ,  Josef S. Watts

IPC: H01L21/70 ,  H01L29/786 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/78642 ,  H01L21/76829 ,  H01L21/823412 ,  H01L29/66643 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66833

Abstract: The disclosure provides a vertical FinFET structure, including: a substrate including a first source/drain region; a looped channel region positioned on the first source/drain region of the substrate, the looped channel region having an inner perimeter which surrounds a hollow interior of the looped channel region; a first gate positioned within the hollow interior of the looped channel region, wherein the first gate is formed onto the looped channel region along the inner perimeter of the looped channel region; and a second source/drain region positioned on and overlying an upper surface of the looped channel region.

公开(公告)号：US10062689B2

公开(公告)日：2018-08-28

申请号：US15154087

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shesh Mani Pandey

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/51 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823487 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7834

Abstract: A FinFET-type device is formed having a fin structure with vertically-oriented source/drain regions (with lightly doped extensions) and a channel region extending substantially perpendicular to the surface of the semiconductor substrate. A semiconductor stack is provided (or formed) having a first heavily doped layer and two lightly doped layer, with a channel region formed between the two lightly doped layers. The stack is etched to form fin structures (for the devices) and a gate stack is formed along the sidewalls of the channel region. A second heavily doped layer is selectively formed on the upper lightly doped layer. A portion of the first heavily doped layer and a portion of the lower lightly doped layer form a lower S/D region with a lightly doped extension region. Similarly, a portion of the second heavily doped layer and a portion of the upper lightly doped layer form an upper S/D region with a lightly doped extension region.