公开(公告)号：US09812324B1

公开(公告)日：2017-11-07

申请号：US15405789

申请日：2017-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Zhuang ,  Lars Liebmann ,  Stuart A. Sieg ,  Fee Li Lie ,  Mahender Kumar ,  Shreesh Narasimha ,  Ahmed Hassan ,  Guillaume Bouche ,  Xintuo Dai

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/30 ,  H01L21/027 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/308 ,  H01L21/28 ,  H01L21/3065

CPC classification number: H01L27/0207 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes providing a semiconductor structure having a substrate including a longitudinally extending plurality of fins formed thereon. A target layout pattern is determined, which overlays active areas devices disposed on the fins. The target layout pattern includes a first group of sections overlaying devices having more fins than adjacent devices and a second group of sections overlaying devices having less fins than adjacent devices. A first extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the first group toward adjacent sections of the first group. A second extended exposure pattern is patterned into the structure, and includes extensions that extend sections of the second group toward adjacent sections of the second group. Portions of the first and second extended exposure patterns are combined to form a final pattern overlaying the same active areas as the target pattern.

公开(公告)号：US09780002B1

公开(公告)日：2017-10-03

申请号：US15173766

申请日：2016-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Brian Greene ,  Mahender Kumar ,  Daniel J. Dechene ,  Daniel Jaeger

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/02 ,  H01L21/027 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/3065 ,  H01L21/762 ,  H01L29/66 ,  H01L27/092 ,  H01L27/02

CPC classification number: H01L21/26506 ,  H01L21/02118 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0271 ,  H01L21/0276 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31155 ,  H01L21/76213 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/66803

Abstract: Methodologies for patterning and implantation are provided Embodiments include forming fins; forming an SiN over the fins; forming an a-Si layer over the SiN; forming and patterning a first patterning layer over the a-Si layer; etching through the a-Si layer using the first patterning layer as a mask; removing the first patterning layer; implanting ions in exposed groups of fins; forming and patterning a second patterning layer to expose a first group of fins and a portion of the a-Si layer on opposite sides of the first group of fins; implanting ions in a first region of the first group of fins; forming a third patterning layer over the first region of the first group of fins and exposing a second region of the first group of fins; and implanting ions in the second region of the first group of fins.

公开(公告)号：US09698018B1

公开(公告)日：2017-07-04

申请号：US15132589

申请日：2016-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Haigou Huang ,  Jinping Liu

IPC: H01L21/225 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/2255 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795

Abstract: A method of introducing self-aligned dopants in semiconductor fins and the resulting device are provided. Embodiments include providing semiconductor fins on first and second portions of a substrate; forming a BSG layer on side surfaces of the semiconductor fins on the first portion of the substrate; forming a first SiN layer on the BSG layer; forming a high quality oxide layer over an upper surface of the substrate, the first SiN layer and side surfaces of the semiconductor fins on the second portion of the substrate; forming a PSG layer over the high quality oxide layer on the second portion of the substrate and side surfaces of the semiconductor fins on the second portion of the substrate; and forming a second SiN layer over the high quality oxide layer and the PSG layer.

公开(公告)号：US09640402B1

公开(公告)日：2017-05-02

申请号：US15049351

申请日：2016-02-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Jiong Li

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/40

CPC classification number: H01L21/283 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/32139 ,  H01L29/401 ,  H01L29/4238 ,  H01L29/513

Abstract: Methods for forming a gate structure of a circuit structure are provide. The methods for forming the gate structure may include: forming a first gate pattern in a gate mask layer, the forming including a first etching of rounded corner portions of the first gate pattern; forming a second gate pattern in the gate mask layer, the second gate pattern at least partially overlapping the first gate pattern, the forming including a second etching of rounded corner portions of the second gate pattern; and, etching the gate mask layer using the first gate pattern and second gate pattern to form the gate structure.

公开(公告)号：US09620380B1

公开(公告)日：2017-04-11

申请号：US14972804

申请日：2015-12-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xintuo Dai ,  Huang Liu ,  Jin Ping Liu ,  Jiong Li

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/033 ,  H01L27/108

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/10826 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method for fabricating an integrated circuit includes providing an semiconductor wafer includes forming in an upper mandrel layer a first upper mandrel having a first critical dimension and a second upper mandrel having a second critical dimension; forming upper sidewall spacers along sidewalls of the first upper mandrel while leaving the second upper mandrel without sidewall spacers; removing the first upper mandrel from between the upper sidewall spacers; transferring a pattern of the upper sidewall spacers and of the second upper mandrel into a lower mandrel layer to form first lower mandrels according to the pattern of the upper sidewall spacers and a second lower mandrel according to the pattern of the second upper mandrel; and forming lower sidewall spacers along sidewalls of the first and second lower mandrels.