公开(公告)号：US09209181B2

公开(公告)日：2015-12-08

申请号：US13918536

申请日：2013-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara G. Reddy Vakada ,  Laegu Kang ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Srikanth Balaji Samavedam ,  Sri Charan Vemula ,  Manfred Eller

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0928

Abstract: A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.

Abstract translation: 一种方法包括在N-有源区上形成一层硅 - 碳，进行公共沉积工艺，以在硅 - 碳层和P-活性区上形成第一半导体材料层， 在P活性区域中的第一半导体材料上形成第二半导体材料层，形成N型和P型晶体管。 一种器件包括位于N-有源区上的硅碳层，位于硅碳层上的第一半导体的第一层，位于P活性区上的第一半导体材料的第二层， 位于第一半导体材料的第二层上的第二半导体材料的层，以及N型和P型晶体管。

公开(公告)号：US08916442B2

公开(公告)日：2014-12-23

申请号：US13743886

申请日：2013-01-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara Govindeswara Reddy Vakada ,  Laegu Kang ,  Michael P. Ganz ,  Yi Qi ,  Puneet Khanna ,  Sri Charan Vemula ,  Srikanth Samavedam

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L29/167 ,  H01L21/2205 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L29/04 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66651

Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.

Abstract translation: 公开了一种使得能够形成具有能够抑制阈值电压变化的结果信道分布和所得到的器件的诸如SSRW FET的器件的陡峭通道轮廓的方法。 实施例包括在硅晶片中提供STI区域; 在STI区域之间对硅晶片进行深阱注入掺杂剂; 在所述STI区域之间的所述掺杂硅晶片中形成凹部; 在所述凹部中进行所述掺杂剂的浅阱注入到所述硅晶片中; 并在凹陷中的掺杂硅晶片上形成Si：C。

公开(公告)号：US10680065B2

公开(公告)日：2020-06-09

申请号：US16052140

申请日：2018-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George R. Mulfinger ,  Timothy J. McArdle ,  Jody Fronheiser ,  El Mehdi Bazizi ,  Yi Qi

IPC: H01L29/10 ,  H01L29/08 ,  H01L27/12 ,  H01L29/165 ,  H01L21/84 ,  H01L21/02 ,  H01L21/308 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/027 ,  H01L29/786

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is arranged laterally between a first source/drain region and a second source/drain region. The channel region includes a first semiconductor layer and a second semiconductor layer arranged over the first semiconductor layer. A gate structure is arranged over the second semiconductor layer of the channel region The first semiconductor layer is composed of a first semiconductor material having a first carrier mobility. The second semiconductor layer is composed of a second semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.

公开(公告)号：US20190280105A1

公开(公告)日：2019-09-12

申请号：US15916323

申请日：2018-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Qun Gao ,  Jerome Ciavatti ,  Yi Qi ,  Wei Hong ,  Yongjun Shi ,  Jae Gon Lee ,  Chun Yu Wong

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.

公开(公告)号：US20190221515A1

公开(公告)日：2019-07-18

申请号：US15872589

申请日：2018-01-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Jianwei Peng ,  Xusheng Wu ,  Yi Qi ,  Jeffrey Chee

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.

公开(公告)号：US10355104B2

公开(公告)日：2019-07-16

申请号：US15795833

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Sang Woo Lim ,  Kyung-Bum Koo ,  Alina Vinslava ,  Pei Zhao ,  Zhenyu Hu ,  Hsien-Ching Lo ,  Joseph F. Shepard, Jr. ,  Shesh Mani Pandey

IPC: H01L21/02 ,  H01L21/84 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

公开(公告)号：US10297675B1

公开(公告)日：2019-05-21

申请号：US15795879

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC: H01L21/84 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US10164010B1

公开(公告)日：2018-12-25

申请号：US15798546

申请日：2017-10-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Hong ,  Hsien-Ching Lo ,  Haiting Wang ,  Yanping Shen ,  Yi Qi ,  Yongjun Shi ,  Hui Zang ,  Edward Reis

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

Abstract: Methods form integrated circuit structures that include a semiconductor layer having at least one fin. At least three gate stacks contact, and are spaced along, the top of the fin. An insulator in trenches in the fin contacts the first and third of the gate stacks, and extends into the fin from the first and third gate stacks. Source and drain regions in the fin are adjacent a second of the gate stacks. The second gate stack is between the first and third gate stacks along the top of the fin. Additionally, a protective liner is in the trench between a top portion of the insulator a bottom portion of the insulator.

公开(公告)号：US10068810B1

公开(公告)日：2018-09-04

申请号：US15697661

申请日：2017-09-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Sipeng Gu

IPC: H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/308

Abstract: A method of forming semiconductor fins having different fin heights and which are dielectrically isolated from an underlying semiconductor substrate. The fins may be formed by etching an active epitaxial layer that is disposed over the substrate. An intervening sacrificial epitaxial layer may be used to template growth of the active epitaxial layer, and is then removed and backfilled with an isolation dielectric layer. The isolation dielectric layer may be disposed between bottom surfaces of the fins and the substrate, and may be deposited, for example, following the etching process used to define the fins. Within different regions of the substrate, dielectrically isolated fins of different heights may have substantially co-planar top surfaces.

公开(公告)号：US09837268B2

公开(公告)日：2017-12-05

申请号：US15154444

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Xunyuan Zhang ,  Catherine B. Labelle

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02532 ,  H01L21/02639 ,  H01L21/311 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.