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    FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION
    22.
    发明申请
    FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION 有权
    场效应晶体管和制造方法

    公开(公告)号：US20150001642A1

    公开(公告)日：2015-01-01

    申请号：US14476073

    申请日：2014-09-03

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hoon Kim ,  Kisik Choi ,  Chanro Park

    IPC: H01L29/49 ,  H01L29/423

    CPC classification number: H01L29/4966 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

    Abstract: An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.

    Abstract translation: 公开了一种改进的场效应晶体管及其制造方法。 在栅腔的基底和侧壁中形成阻挡层堆叠。 阻挡层堆叠具有第一金属层和第二金属层。 栅极电极金属沉积在空腔中。 阻挡层堆叠在栅极腔的侧壁上变薄或去除，以更精确地控制场效应晶体管的电压阈值。

    METHODS OF SCALING THICKNESS OF A GATE DIELECTRIC STRUCTURE, METHODS OF FORMING AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUITS
    25.
    发明申请
    METHODS OF SCALING THICKNESS OF A GATE DIELECTRIC STRUCTURE, METHODS OF FORMING AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUITS 有权
    门型电介质结构厚度方法，形成集成电路的方法和集成电路

    公开(公告)号：US20150129972A1

    公开(公告)日：2015-05-14

    申请号：US14080533

    申请日：2013-11-14

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Kisik Choi

    IPC: H01L21/02 ,  H01L27/092 ,  H01L29/51 ,  H01L21/28

    CPC classification number: H01L29/512 ,  H01L21/28185 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517

    Abstract: Methods of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate, methods of forming an integrated circuit, and integrated circuits are provided. A method of scaling thickness of a gate dielectric structure that overlies a semiconductor substrate includes providing the semiconductor substrate. An interfacial oxide layer is formed in or on the semiconductor substrate. A high-k dielectric layer is formed over the interfacial oxide layer. An oxygen reservoir is formed over at least a portion of the high-k dielectric layer. A sealant layer is formed over the oxygen reservoir. The semiconductor substrate including the oxygen reservoir disposed thereon is annealed to diffuse oxygen through the high-k dielectric layer and the interfacial oxide layer from the oxygen reservoir. Annealing extends the interfacial oxide layer into the semiconductor substrate at portions of the semiconductor substrate that underlie the oxygen reservoir to form a regrown interfacial region in or on the semiconductor substrate.

    Abstract translation: 提供了覆盖半导体衬底的栅介质结构的厚度缩小方法，形成集成电路的方法和集成电路。 覆盖半导体衬底的栅介质结构的厚度缩小方法包括提供半导体衬底。 在半导体衬底中或其上形成界面氧化物层。 在界面氧化物层上形成高k电介质层。 在高k电介质层的至少一部分上形成氧储存器。 在氧储存器上形成密封剂层。 包括设置在其上的氧气储存器的半导体基板被退火以通过高k电介质层和来自氧气存储器的界面氧化物层扩散氧。 退火在半导体衬底的位于氧储存器底部的部分处将界面氧化物层延伸到半导体衬底中，以在半导体衬底中或其上形成再生长界面区域。

    METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS
    26.
    发明申请
    METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS 有权
    用于CMOS应用和结果产品的晶体管器件的门结构的方法

    公开(公告)号：US20150061027A1

    公开(公告)日：2015-03-05

    申请号：US14017485

    申请日：2013-09-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhendong Hong ,  Susie Tzeng ,  Amol Joshi ,  Ashish Bodke ,  Divya Pisharoty ,  Usha Raghuram ,  Olov Karlsson ,  Kisik Choi ,  Salil Mujumdar ,  Paul R. Besser ,  Jinping Liu ,  Hoon Kim

    IPC: H01L27/092 ,  H01L21/28

    CPC classification number: H01L27/0922 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545

    Abstract: One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.

    Abstract translation: 用于形成用于NMOS和PMOS晶体管的替代栅极结构的一种方法包括执行蚀刻工艺以去除用于NMOS和PMOS晶体管的牺牲栅极结构，由此限定NMOS和PMOS栅极腔，在栅极腔中沉积栅极绝缘层， 在栅极腔中的栅极绝缘层上的第一金属层，执行至少一个处理操作以在NMOS栅极腔内的第一金属层上方形成（1）NMOS金属硅化物材料，所述NMOS金属硅化物材料具有第一量 原子硅，和（2）在PMOS栅极腔内的第一金属层上方的PMOS金属硅化物材料，PMOS金属硅化物材料具有第二量的原子硅，并且其中第一和第二量的原子硅是不同的，以及 在NMOS和PMOS门腔内形成栅极盖层。

    REPLACEMENT METAL GATE WITH MULITIPLE TITANIUM NITRIDE LATERS
    27.
    发明申请
    REPLACEMENT METAL GATE WITH MULITIPLE TITANIUM NITRIDE LATERS 审中-公开
    更换金属盐与多余的硝酸钛后期

    公开(公告)号：US20140246734A1

    公开(公告)日：2014-09-04

    申请号：US13782106

    申请日：2013-03-01

    Applicant: Globalfoundries Inc.

    Inventor： Hoon Kim ,  Kisik Choi

    IPC: H01L29/51 ,  H01L29/49 ,  H01L21/28

    CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

    Abstract: A semiconductor comprising a multilayer structure which prevents oxidization of the titanium nitride layer that protects a high-K dielectric layer is provided. Replacement metal gates are over the multilayer structure. A sacrificial polysilicon gate structure is deposited first. The sacrificial polysilicon gate structure is then removed, and the various layers of the replacement metal gate structure are deposited in the space previously occupied by the sacrificial polysilicon gate structure.

    Abstract translation: 提供了包括防止保护高K电介质层的氮化钛层的氧化的多层结构的半导体。 替代金属门在多层结构之上。 首先沉积牺牲多晶硅栅极结构。 然后去除牺牲多晶硅栅极结构，并且替换金属栅极结构的各个层沉积在先前由牺牲多晶硅栅极结构占据的空间中。

    SEMICONDUCTOR GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION AND METHOD OF MAKING SAME
    28.
    发明申请
    SEMICONDUCTOR GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION AND METHOD OF MAKING SAME 有权
    用于阈值电压调节的半导体闸门结构及其制造方法

    公开(公告)号：US20140231922A1

    公开(公告)日：2014-08-21

    申请号：US13770493

    申请日：2013-02-19

    Applicant: GLOBALFOUNDRIES, INC.

    Inventor： Hoon Kim ,  Kisik Choi

    IPC: H01L29/40 ,  H01L29/49

    CPC classification number: H01L29/401 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

    Abstract: A gate structure of a semiconductor device having a NFET and a PFET, includes a lower layer of a hafnium-based dielectric over the gates of the NFET and PFET, and an upper layer of a lanthanide dielectric. The dielectrics are annealed to mix them above the NFET resulting in a lowered work function, and corresponding threshold voltage reduction. An annealed, relatively thick titanium nitride cap over the mixed dielectric above the NFET gate also lowers the work function and threshold voltage. Above the TiN cap and the hafnium-based dielectric over the PFET gate, is another layer of titanium nitride that has not been annealed. A conducting layer of tungsten covers the structure.

    Abstract translation: 具有NFET和PFET的半导体器件的栅极结构包括在NFET和PFET的栅极上方的基于铪的电介质的下层和镧系元素电介质的上层。 将电介质退火以将其混合在NFET上方，导致降低的功函数和相应的阈值电压降低。 在NFET栅极上方的混合电介质上的退火的较厚的氮化钛盖也降低了功函数和阈值电压。 在PFET栅极上的TiN盖和铪基电介质之上，是未经退火的另一层氮化钛。 钨的导电层覆盖该结构。

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