公开(公告)号：US20200285954A1

公开(公告)日：2020-09-10

申请号：US16464977

申请日：2018-06-07

Applicant: Huazhong University of Science and Technology

Inventor： Yi LI ,  Wenqian PAN ,  Xiangshui MIAO

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: The present disclosure discloses a memory-based CNN, comprising: an input module, a convolution layer circuit module, a pooling layer circuit module, an activation function module, a fully connected layer circuit module, a softmax function module and an output module, convolution kernel values or synapse weights are stored in the NOR FLASH units; the input module converts an input signal into a voltage signal required by the convolutional neural network; the convolutional layer circuit module convolves the voltage signal corresponding to the input signal with the convolution kernel values, and transmits the result to the activation function module; the activation function module activates the signal; the pooling layer circuit module performs a pooling operation on the activated signal; the fully connected layer circuit module multiplies the pooled signal with the synapse weights to achieve classification; the softmax function module normalizes the classification result into probability values as an output of the entire network. The disclosure satisfies the requirements of real-time data processing and has low hardware cost.

公开(公告)号：US20250113505A1

公开(公告)日：2025-04-03

申请号：US18285857

申请日：2023-05-06

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Hao TONG ,  Binhao WANG ,  Shaojie LONG ,  Xiangshui MIAO

IPC: H10B41/27 ,  H10B41/30 ,  H10B41/40

Abstract: The invention discloses a three-dimensional 1S1C memory based on a ring capacitor and a preparation method. The memory includes: a horizontal peripheral electrode layer including a first dielectric layer and a first metal electrode layer alternately stacked and grown on a substrate and provided with trenches penetrating in a vertical direction and holes penetrating in the vertical direction, a vertical functional layer, and a capacitive dielectric layer. An annular groove is disposed outside each hole. The annular groove surrounds the holes and vertically cuts off the peripheral electrode layer. The annular groove is evenly filled with a capacitive dielectric layer. A top of the second metal electrode layer is extended to a surface of a topmost first dielectric layer to form a bit line electrode and is connected to a bit line. A region where the second metal electrode layer faces the first metal electrode layer forms a memory cell.

公开(公告)号：US20240371438A1

公开(公告)日：2024-11-07

申请号：US18031356

申请日：2022-07-07

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Xingsheng WANG ,  Yinghao MA ,  Fan Yang ,  Chengxu WANG ,  Menghua HUANG ,  Xiangshui MIAO

IPC: G11C13/00

Abstract: A high-speed and large-current adjustable pulse circuit, an operating circuit and an operating method of a phase-change memory are provided. The high-speed and large-current adjustable pulse circuit is provided with a clamping structure, a current mirror structure and a leakage current shutdown structure. The clamping structure including a clamping operational amplifier and a first MOS transistor is configured to generate a reference current. The current mirror structure is configured to generate an output current proportional to the reference current. The leakage current shutdown structure is configured to turn off the current mirror structure and reduce leakage current when pulse disappear. In this way, a device with an adjustable current and a reduced leakage current is realized.

公开(公告)号：US20240319563A1

公开(公告)日：2024-09-26

申请号：US18577702

申请日：2021-09-07

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Xiaomin CHENG ,  Zhuli HE ,  Yunlai ZHU ,  Han LI ,  Xiangshui MIAO

IPC: G02F3/02 ,  G11C13/00 ,  H03K19/173

CPC classification number: G02F3/022 ,  G11C13/0004 ,  H03K19/173

Abstract: A Y-branch type phase-change all-optical Boolean logic device comprises a waveguide of a Y-branch structure and phase change function units covered over the waveguide. In the logic implementation method, a light pulse having a large power is employed to perform a write operation on the phase change function unit, so that the phase change function unit is heated to generate a crystallization or amorphization phase change, thereby causing a difference in optical properties under two states; the state of the phase change function unit is read by employing a light pulse having a small power, and the state of its phase change material is not changed. By defining input logic signals respectively and defining three operation steps, an operation mode reconfigurable logic can be implemented, and all 16 binary Boolean logic calculations are implemented in a simple structure by means of step-by-step operation.

公开(公告)号：US20230301215A1

公开(公告)日：2023-09-21

申请号：US17785916

申请日：2021-08-30

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Yi LI ,  Yuhui HE ,  Yaoyao FU ,  Xiaodi HUANG ,  Xiangshui MIAO

IPC: H10N70/00 ,  H10N70/20 ,  H10B63/00

CPC classification number: H10N70/826 ,  H10B63/22 ,  H10B63/84 ,  H10N70/026 ,  H10N70/245

Abstract: The present invention provides a preparation method of a bipolar gating memristor and a bipolar gating memristor. The preparation method includes: preparing a lower electrode; depositing a resistive material layer on the lower electrode; and depositing an upper electrode on the resistive material layer by using a magnetron sputtering manner to deposit the upper electrode, controlling upper electrode metal particles to have suitable kinetic energy by controlling sputtering power, controlling a vacuum degree of a region where the upper electrode and the resistive material layer are located, such that a redox reaction occurs spontaneously between the upper electrode and the resistive material layer during the deposition of the upper electrode to form a built-in bipolar gating layer; and continuously depositing the upper electrode on the built-in bipolar gating layer .

公开(公告)号：US20230221619A1

公开(公告)日：2023-07-13

申请号：US17910835

申请日：2021-07-22

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Xiaomin CHENG ,  Zhuli HE ,  Yunlai ZHU ,  Han LI ,  Xiangshui MIAO

IPC: G02F3/00

CPC classification number: G02F3/00 ,  G02F2201/307 ,  G02F2203/50 ,  G02F2203/11

Abstract: The disclosure provides a straight waveguide phase change all-photonic Boolean logic device and a full binary logic implementation method thereof, including a straight waveguide structure, a phase change functional unit covered on top of a waveguide and a protective layer thereof, and a waveguide Bragg grating structure. In terms of the logic implementation method, optical pulses are respectively input from two ends of the device to modulate the state of the phase change functional unit. The parameters of the waveguide Bragg grating structure are set to reflect the wavelength of the pump optical pulse, so that write pulses input from the two ends only act on the phase change functional unit closest to that end. A probe optical pulse with a specific wavelength is selected, and the probe light under the wavelength is less reflected by the waveguide Bragg grating and does not affect the reading of the state of the device. The disclosure has advantages such as anti-electromagnetic interference and parallel operation. Functions of 16 types of binary Boolean logic operation are implemented, which greatly improves the work efficiency of logic operation.

公开(公告)号：US20210327505A1

公开(公告)日：2021-10-21

申请号：US16336900

申请日：2018-06-07

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Yi LI ,  Zhuorui WANG ,  Xiangshui MIAO ,  Yaxiong ZHOU ,  Long CHENG

IPC: G11C13/00 ,  H03K19/21 ,  G06F7/48

Abstract: The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

公开(公告)号：US20210043255A1

公开(公告)日：2021-02-11

申请号：US17037655

申请日：2020-09-29

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Xiangshui MIAO ,  Qi LIN ,  Hao TONG

IPC: G11C13/00

Abstract: An operating method for improving the performance of a selector device is provided, including: determining and applying a direct current (DC) or alternating current (AC) operating voltage and a limit current of the selector device, so that the selector device circulates until a off-state resistance is reduced; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is reduced to a minimum value; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is increased; continuously applying the operating voltage and the limit current to the selector device, so that the selector device circulates until the off-state resistance is increased to a maximum value; and adjusting the operating voltage and the limit current, and performing DC or AC operation pulsed operation on a selector.

公开(公告)号：US20150381181A1

公开(公告)日：2015-12-31

申请号：US14849621

申请日：2015-09-10

Applicant: Huazhong University of Science and Technology

Inventor： Xiangshui MIAO ,  Yi LI ,  Yingpeng ZHONG

IPC: H03K19/08 ,  G11C11/16 ,  G11C13/00 ,  H03K19/177

CPC classification number: H03K19/08 ,  G11B5/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0097 ,  H03K19/1776 ,  H03K19/18

Abstract: A non-volatile logic device, including: a substrate, a magnetic head, a base electrode, an insulating layer, a phase-change magnetic film, and a top electrode. The substrate includes a silicon substrate and an active layer attached to the silicon substrate. The base electrode includes an N-type silicon layer, a P-type silicon layer and a heating layer, the N-type silicon layer and the P-type silicon layer constitute a PN diode structure, and the size of the heating layer is smaller than that of the P-type silicon layer. The phase-change magnetic film is deposited on the insulating layer and is electrically contacted with the heating layer. The top electrode and the base electrode are connected to an external electrical pulse signal, and an external magnetic field parallel to a two dimensional plane of the phase-change magnetic film is applied to the non-volatile logic device.

Abstract translation: 一种非易失性逻辑器件，包括：基板，磁头，基极，绝缘层，相变磁性膜和顶部电极。 衬底包括硅衬底和附着到硅衬底的有源层。 基极包括N型硅层，P型硅层和加热层，N型硅层和P型硅层构成PN二极管结构，加热层的尺寸较小 比P型硅层高。 相变磁性膜沉积在绝缘层上并与加热层电接触。 顶部电极和基极连接到外部电脉冲信号，并且将平行于相变磁性膜的二维平面的外部磁场施加到非易失性逻辑器件。

公开(公告)号：US20150236697A1

公开(公告)日：2015-08-20

申请号：US14706004

申请日：2015-05-07

Applicant: Huazhong University of Science and Technology

Inventor： Xiangshui MIAO ,  Yi LI ,  Yingpeng ZHONG ,  Lei XU ,  Huajun SUN ,  Xiaomin CHENG

IPC: H03K19/003 ,  H03K19/177 ,  H03K19/20 ,  G11C13/00 ,  H03K19/173

CPC classification number: H03K19/00346 ,  G11C13/0004 ,  G11C13/004 ,  H03K19/1733 ,  H03K19/17724 ,  H03K19/20

Abstract: A nonvolatile logic gate circuit based on phase change memories, including a first phase change memory, a second phase change memory, a first controllable switch element and a first resistor, wherein a first end of the first phase change memory serves as a first input end of an AND gate circuit, a first end of the second phase change memory serves as a second input end of the AND gate circuit, a first end of the first controllable switch element is connected to a second end of the first phase change memory, a second end of the first controllable switch element is grounded; one end of the first resistor is connected to the first end of the second phase change memory, the other end of the first resistor is grounded; and the first end of the second phase change memory serves as an output end of the AND gate circuit.

Abstract translation: 一种基于相变存储器的非易失性逻辑门电路，包括第一相变存储器，第二相变存储器，第一可控开关元件和第一电阻器，其中第一相变存储器的第一端用作第一输入端 和门电路的第一端，第二相变存储器的第一端用作与门电路的第二输入端，第一可控开关元件的第一端连接到第一相变存储器的第二端， 第一可控开关元件的第二端接地; 第一电阻器的一端连接到第二相变存储器的第一端，第一电阻器的另一端接地; 并且第二相变存储器的第一端用作与门电路的输出端。