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41 条记录 (耗时 0.057 秒)

    Methods for a gate replacement process
    21.
    发明授权
    Methods for a gate replacement process 有权
    门更换过程的方法

    公开(公告)号：US08367563B2

    公开(公告)日：2013-02-05

    申请号：US12575280

    申请日：2009-10-07

    申请人： Matt Yeh ,  Hui Ouyang ,  Da-Yuan Lee ,  Kuang Yuan Hsu ,  Hun-Jan Tao ,  Xiong-Fei Yu

    发明人： Matt Yeh ,  Hui Ouyang ,  Da-Yuan Lee ,  Kuang Yuan Hsu ,  Hun-Jan Tao ,  Xiong-Fei Yu

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/401 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66545

    摘要： A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.

    摘要翻译： 公开了一种制造半导体器件的方法。 在一个实施例中，该方法可以包括提供衬底; 在所述衬底上形成包括第一虚拟栅极的栅极结构; 从栅极结构去除第一伪栅极以形成沟槽; 形成界面层，高k电介质层和覆盖层以部分地填充在沟槽中; 在所述覆盖层上形成第二虚拟栅极，其中所述第二伪栅极填充所述沟槽; 并用金属栅极替换第二虚拟栅极。 在一个实施例中，该方法可以包括提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在所述高k电介质层上形成蚀刻停止层; 在所述蚀刻停止层上形成包括低热预算硅的覆盖层; 在覆盖层上形成虚拟栅极层; 形成栅极结构; 并进行门更换处理。

    INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME
    23.
    发明申请
    INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME 有权
    具有良好控制的表面接近度的集成电路装置及其制造方法

    公开(公告)号：US20120273847A1

    公开(公告)日：2012-11-01

    申请号：US13543943

    申请日：2012-07-09

    申请人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

    发明人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

    IPC分类号： H01L27/085

    CPC分类号： H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

    摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit devices. An exemplary integrated circuit device achieved by the method has a surface proximity of about 1 nm to about 3 nm and a tip depth of about 5 nm to about 10 nm. The integrated circuit device having such surface proximity and tip depth includes an epi source feature and an epi drain feature defined by a first facet and a second facet of a substrate in a first direction, such as a {111} crystallographic plane of the substrate, and a third facet of the substrate in a second direction, such as a { 100} crystallographic plane of the substrate.

    摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 通过该方法实现的示例性集成电路器件具有约1nm至约3nm的表面接近度和约5nm至约10nm的尖端深度。 具有这种表面接近度和尖端深度的集成电路器件包括由第一方向（例如衬底的{111}晶体平面）的第一方向上的第一面和第二小面限定的外延源特征和外延漏极特征， 以及在第二方向上的衬底的第三面，例如衬底的{100}晶面。

    Methods for forming metal gate transistors
    24.
    发明授权
    Methods for forming metal gate transistors 有权
    形成金属栅晶体管的方法

    公开(公告)号：US08268085B2

    公开(公告)日：2012-09-18

    申请号：US12719532

    申请日：2010-03-08

    申请人： Matt Yeh ,  Shun Wu Lin ,  Hui Ouyang

    发明人： Matt Yeh ,  Shun Wu Lin ,  Hui Ouyang

    IPC分类号： B08B3/04

    CPC分类号： H01L21/02068 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    摘要： A method for cleaning a diffusion barrier over a gate dielectric of a metal-gate transistor over a substrate is provided. The method includes cleaning the diffusion barrier with a first solution including at least one surfactant. The amount of the surfactant of the first solution is about a critical micelle concentration (CMC) or more. The diffusion barrier is cleaned with a second solution. The second solution has a physical force to remove particles over the diffusion barrier. The second solution is substantially free from interacting with the diffusion barrier.

    摘要翻译： 提供了一种在衬底上清洁金属栅极晶体管的栅极电介质上的扩散阻挡层的方法。 该方法包括用包含至少一种表面活性剂的第一溶液清洗扩散阻挡层。 第一溶液的表面活性剂的量约为临界胶束浓度（CMC）或更高。 扩散阻挡层用第二种溶液清洗。 第二种解决方案具有去除扩散阻挡层上的颗粒的物理力。 第二溶液基本上不与扩散阻挡层相互作用。

    Method of manufacturing integrated circuit device with well controlled surface proximity
    29.
    发明授权
    Method of manufacturing integrated circuit device with well controlled surface proximity 有权
    具有良好控制表面接近性的集成电路器件的制造方法

    公开(公告)号：US08216906B2

    公开(公告)日：2012-07-10

    申请号：US12827344

    申请日：2010-06-30

    申请人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

    发明人： Ming-Huan Tsai ,  Hui Ouyang ,  Chun-Fai Cheng ,  Wei-Han Fan

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/823814 ,  H01L29/7848

    摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a lightly doped source and drain (LDD) region that acts as an etch stop. The LDD region may act as an etch stop during an etching process implemented to form a recess in the substrate that defines a source and drain region of the device.

    摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过形成用作蚀刻停止的轻掺杂源极和漏极（LDD）区域来实现改进的控制。 LDD区域可以在蚀刻工艺期间用作蚀刻停止层，以在衬底中形成限定器件的源极和漏极区域的凹陷。