公开(公告)号：US20160027876A1

公开(公告)日：2016-01-28

申请号：US14709696

申请日：2015-05-12

Applicant: IMEC VZW ,  SAMSUNG ELECTRONICS CO. LTD.

Inventor： Seung Hun Lee ,  Geert Eneman

IPC: H01L29/10 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41783 ,  H01L29/7848 ,  H01L29/7849

Abstract: A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.

Abstract translation: 公开了CMOS半导体FinFET器件和用于制造CMOS半导体FinFET器件的方法。 器件可以包括在包含SiGe的公共应变松弛缓冲层上具有包含Ge的沟道区的nFinFET和pFinFET。 通道区中Ge的浓度高于应变松弛缓冲层中Ge的浓度。 器件还包括用于nFinFET的源极/漏极区域，源极/漏极区域包括SiGe; 以及用于pFinFET的源极/漏极区域，第二源极/漏极区域包括Ge。

公开(公告)号：US09064702B2

公开(公告)日：2015-06-23

申请号：US13956273

申请日：2013-07-31

Applicant: IMEC ,  GLOBALFOUNDRIES INC.

Inventor： David Brunco ,  Geert Eneman

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/02 ,  H01L29/78 ,  H01L21/324

CPC classification number: H01L21/02565 ,  H01L21/0243 ,  H01L21/02521 ,  H01L21/02664 ,  H01L21/324 ,  H01L29/7843

Abstract: A method for reducing defects in an active device area of a semiconductor device during fabrication is disclosed. In one aspect, the method comprises providing the active device area adjacent an isolation structure, wherein a substantially planar surface is formed over the isolation structure and the active device area, forming a patterned stress-inducing layer over the substantially planar surface, forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, where the screening layer is configured to screen part of the stress field induced by the patterned stress-inducing layer, performing an anneal process after forming the patterned stress-inducing layer on the substantially planar surface, so as to induce a movement of the defects towards a contact interface between the active device area and the isolation structure, and removing the patterned stress-inducing layer from the substantially planar surface.

Abstract translation: 公开了一种用于在制造期间减少半导体器件的有源器件区域中的缺陷的方法。 在一个方面，该方法包括提供邻近隔离结构的有源器件区域，其中基本平坦的表面形成在隔离结构和有源器件区域之上，在基本平坦的表面上形成图案化的应力诱导层，至少形成 在图案化的应力诱导层和基本上平坦的表面之间的一个屏蔽层，其中屏蔽层被配置为屏蔽由图案化的应力诱导层感应的应力场的一部分，在形成图案化的应力诱导层之后执行退火工艺 在基本上平坦的表面上，以引起缺陷朝向有源器件区域和隔离结构之间的接触界面的移动，以及从基本平坦的表面移除图案化的应力诱导层。

公开(公告)号：US20140151766A1

公开(公告)日：2014-06-05

申请号：US14086486

申请日：2013-11-21

Applicant: IMEC

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract translation: 提供FinFET器件和制造FinFET器件的方法。 示例性装置可以包括包括至少两个翅片结构的基板。 所述至少两个翅片结构中的每一个可以与源极和漏极区域接触，并且所述至少两个鳍结构中的每一个可以包括覆盖并与衬底接触的应变松弛缓冲器（SRB），并且上层覆盖和 与SRB联系。 可以选择上层和SRB的组成，使得第一鳍结构的上层在生长状态下经受第一迁移率增强应变，第一迁移率增强应变沿纵向施加于 源极区到漏极区，并且其中第二鳍结构的上层的至少上部被应变松弛。

公开(公告)号：US20210336002A1

公开(公告)日：2021-10-28

申请号：US17240694

申请日：2021-04-26

Applicant: IMEC VZW

Inventor： Roger Loo ,  Geert Eneman ,  Clement Porret

IPC: H01L29/06 ,  H01L29/167 ,  H01L29/78

Abstract: A semiconductor structure including a semiconductor substrate having a top surface, one or more group IV semiconductor monocrystalline nanostructures, each having a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a non-zero distance, each nanostructure having a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The epitaxial source and drain structures are made of a group IV semiconductor doped with one or more of Sb and Bi, and optionally one or more of As and P, thereby creating tensile strain in the group IV semiconductor monocrystalline nanostructure.

公开(公告)号：US20200212205A1

公开(公告)日：2020-07-02

申请号：US16719852

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Geert Eneman ,  Bartlomiej PAWLAK ,  Liesbeth WITTERS ,  Geoffrey POURTOIS

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/161 ,  H01L29/78

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

公开(公告)号：US09633891B2

公开(公告)日：2017-04-25

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/32 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

公开(公告)号：US09437681B2

公开(公告)日：2016-09-06

申请号：US14709696

申请日：2015-05-12

Applicant: IMEC VZW ,  Samsung Electronics Co. Ltd.

Inventor： Seung Hun Lee ,  Geert Eneman

IPC: H01L21/70 ,  H01L29/10 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41783 ,  H01L29/7848 ,  H01L29/7849

Abstract: A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.

Abstract translation: 公开了CMOS半导体FinFET器件和用于制造CMOS半导体FinFET器件的方法。 器件可以包括在包含SiGe的公共应变松弛缓冲层上具有包含Ge的沟道区的nFinFET和pFinFET。 通道区中Ge的浓度高于应变松弛缓冲层中Ge的浓度。 器件还包括用于nFinFET的源极/漏极区域，源极/漏极区域包括SiGe; 以及用于pFinFET的源极/漏极区域，第二源极/漏极区域包括Ge。

公开(公告)号：US20160126131A1

公开(公告)日：2016-05-05

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/32

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

Abstract translation: 一个示例性方法包括在由相邻STI结构限定的沟槽中提供层堆叠，并使邻近层堆叠的STI结构凹陷，从而暴露层堆叠的上部，上部至少包括沟道部分。 该方法还包括在层堆叠的上部提供一个或多个保护层，然后进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分。 并且该方法包括去除层堆叠的中心部分，导致层叠体的独立上部和下部在物理上彼此分离。

公开(公告)号：US09117777B2

公开(公告)日：2015-08-25

申请号：US14106699

申请日：2013-12-13

Applicant: IMEC

Inventor： Benjamin Vincent ,  Geert Eneman

IPC: H01L21/322 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L21/3225 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.

Abstract translation: 公开了一种用于从有源层减少缺陷的方法。 有源层可以是半导体器件中的半导体的一部分。 有源层可以至少由隔离结构侧向限定，并且可以在接触界面物理地接触隔离结构。 隔离结构和有源层可以邻接在共同的基本平坦的表面上。 该方法可以包括在共同的基本上平坦的表面上提供图案化的应力诱导层。 应力诱导层可以适于在活性层中诱导应力场，并且感应应力场可能导致活性层中缺陷的剪切应力。 该方法还可以包括在将图案化的应力诱导层提供在共同的基本平坦的表面上之后执行退火步骤。 该方法可以另外包括从共同的基本平坦的表面去除图案化的应力诱导层。

公开(公告)号：US09006705B2

公开(公告)日：2015-04-14

申请号：US13914514

申请日：2013-06-10

Applicant: IMEC ,  GLOBALFOUNDRIES Inc.

Inventor： Geert Eneman ,  David Brunco ,  Geert Hellings

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/775 ,  H01L29/778 ,  H01L29/161 ,  H01L29/165 ,  H01L29/10 ,  B82Y10/00

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/775 ,  H01L29/7781

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract translation: 所公开的技术涉及具有用于载流子限制的应变量子阱的晶体管及其制造方法。 在一个方面，FinFET或平面FET器件包括半导体衬底，形成在半导体衬底上的Ge的应变松弛缓冲层，形成在应变弛缓缓冲层上的沟道层和包含SiGe的应变量子势垒层 介于与应变松弛缓冲层和沟道层接触之间。 应变松弛缓冲层，应变量子势垒层和沟道层的组成被选择为使得沟道层的带偏移和应变量子势垒层的带偏移相对于应变松弛具有相反的符号 缓冲层。