公开(公告)号：US10367031B2

公开(公告)日：2019-07-30

申请号：US15701743

申请日：2017-09-12

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Anne Vandooren ,  Nadine Collaert

IPC: H01L23/40 ,  H01L27/148 ,  H01L21/768 ,  H01L21/822 ,  H01L27/06 ,  H01L29/417 ,  H01L31/0216 ,  H01L21/8258 ,  B28D1/00 ,  H01L21/304 ,  H01L31/0224

Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.

公开(公告)号：US20190081156A1

公开(公告)日：2019-03-14

申请号：US16119132

申请日：2018-08-31

Applicant: IMEC VZW

Inventor： Anabela Veloso ,  Geert Eneman ,  Nadine Collaert ,  Erik Rosseel

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08

Abstract: A device and method for forming a vertical channel device is disclosed. The method includes: forming a vertical semiconductor pillar on a substrate, the vertical semiconductor pillar including a first pillar section, a second pillar section and a third pillar section, wherein the second pillar section is arranged between the first pillar section and the third pillar section and wherein the second pillar section is formed of a material being different from a material forming an upper portion of the first pillar section and different from a material forming a lower portion of the third pillar section; forming a spacer layer on a peripheral surface of the upper portion of the first pillar section and on a peripheral surface of the lower portion of the third pillar section; and forming a gate stack embedding the second pillar section and said upper portion of the first pillar section and said lower portion of the third pillar section, wherein the spacer layer forms a spacer between the gate stack and said upper portion of the first pillar section and between the gate stack and said lower portion of the third pillar section.

公开(公告)号：US20180076260A1

公开(公告)日：2018-03-15

申请号：US15701743

申请日：2017-09-12

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Anne Vandooren ,  Nadine Collaert

IPC: H01L27/148 ,  H01L31/0216 ,  H01L29/417

CPC classification number: H01L27/14875 ,  B28D1/005 ,  H01L21/304 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/0694 ,  H01L29/41708 ,  H01L31/02164 ,  H01L31/022408

Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.

公开(公告)号：US09601488B2

公开(公告)日：2017-03-21

申请号：US15138056

申请日：2016-04-25

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  Clement Merckling ,  Nadine Collaert

IPC: H01L29/41 ,  H01L27/088 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/04 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

公开(公告)号：US20160240532A1

公开(公告)日：2016-08-18

申请号：US15138056

申请日：2016-04-25

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  Clement Merckling ,  Nadine Collaert

IPC: H01L27/088 ,  H01L29/20 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

公开(公告)号：US09324818B2

公开(公告)日：2016-04-26

申请号：US14671134

申请日：2015-03-27

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  Clement Merckling ,  Nadine Collaert

IPC: H01L29/41 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/04 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及栅极全能半导体器件及其制造方法。 一方面，该方法包括在STI区域之间的半导体衬底上提供由源区域和漏极区域锚定的至少一个悬浮纳米结构。 悬浮的纳米结构由与半导体衬底的结晶半导体材料不同的结晶半导体材料形成。 一个栅极叠层围绕至少一个悬浮的纳米结构。

公开(公告)号：US09257539B2

公开(公告)日：2016-02-09

申请号：US14566073

申请日：2014-12-10

Applicant: IMEC VZW

Inventor： Rita Rooyackers ,  Nadine Collaert ,  Geert Eneman

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/20 ,  H01L21/36 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/6681 ,  G10L2015/223 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

Abstract translation: 提供了一种用于制造晶体管器件的方法，包括在衬底上提供多个平行的纳米线; 在所述平行纳米线的中心部分上提供虚拟栅极结构; 外延生长第二材料的延伸部分，选择性地在平行的纳米线上，在中心部分之外; 在所述虚拟栅极结构和所述延伸部分周围和顶部设置填充层; 去除伪栅极结构以产生栅极沟槽，暴露平行纳米线的中心部分; 在所述栅极沟槽的侧壁上提供间隔结构，以限定最终的栅极沟槽; 使平行的纳米线变薄，从而在纳米线和间隔物结构之间产生自由空间; 并且在所述平行的纳米线上或周围选择性地生长量子阱层，至少部分地填充所述自由空间，从而提供所述量子阱层和延伸部分之间的连接。

公开(公告)号：US20150179755A1

公开(公告)日：2015-06-25

申请号：US14566073

申请日：2014-12-10

Applicant: IMEC VZW

Inventor： Rita Rooyackers ,  Nadine Collaert ,  Geert Eneman

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/6681 ,  G10L2015/223 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

Abstract translation: 提供了一种用于制造晶体管器件的方法，包括在衬底上提供多个平行的纳米线; 在所述平行纳米线的中心部分上提供虚拟栅极结构; 外延生长第二材料的延伸部分，选择性地在平行的纳米线上，在中心部分之外; 在所述虚拟栅极结构和所述延伸部分周围和顶部设置填充层; 去除伪栅极结构以产生栅极沟槽，暴露平行纳米线的中心部分; 在所述栅极沟槽的侧壁上提供间隔结构，以限定最终的栅极沟槽; 使平行的纳米线变薄，从而在纳米线和间隔物结构之间产生自由空间; 并且在所述平行的纳米线上或周围选择性地生长量子阱层，至少部分地填充所述自由空间，从而提供所述量子阱层和延伸部分之间的连接。