公开(公告)号：US20180082853A1

公开(公告)日：2018-03-22

申请号：US15273303

申请日：2016-09-22

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech

IPC: H01L21/3105 ,  H01L29/205 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L21/31056 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/31053 ,  H01L21/76229 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/7786

Abstract: In an embodiment, a method of planarising a surface includes applying a first layer to a surface including a protruding region including at least one compound semiconductor and a stop layer on an upper surface such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarised surface including the stop layer on the upper surface of the protruding region and an outer surface of the first layer.

公开(公告)号：US20170372986A1

公开(公告)日：2017-12-28

申请号：US15192283

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/288 ,  H01L21/768 ,  H01L29/78 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/2885 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76846 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/7816 ,  H01L29/7835

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate, a LDMOS transistor arranged in a front surface of the semiconductor substrate and a conductive through substrate via. The conductive through substrate via includes a via extending from the front surface to a rear surface of the semiconductor substrate, a conductive plug filling a first portion of the via and a conductive liner layer lining side walls of a second portion of the via and electrically coupled to the conductive plug.

公开(公告)号：US20170372952A1

公开(公告)日：2017-12-28

申请号：US15192146

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L21/288 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238

Abstract: In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.

公开(公告)号：US20140239411A1

公开(公告)日：2014-08-28

申请号：US13776153

申请日：2013-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Helmut Brech ,  Albert Birner

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L21/823431 ,  H01L23/481 ,  H01L27/1211 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/73 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region.

Abstract translation: 根据本发明的实施例，半导体芯片包括设置在衬底中或衬底上的器件区域，设置在器件区域中的掺杂区域和设置在衬底中的通孔。 通孔延伸穿过掺杂区域。

公开(公告)号：US08815743B2

公开(公告)日：2014-08-26

申请号：US13830185

申请日：2013-03-14

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Uwe Hoeckele ,  Thomas Kunstmann ,  Uwe Seidel

IPC: H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.

Abstract translation: 描述了在形成半导体部件时通过衬底通孔形成的结构和方法。 在一个实施例中，本发明描述了一种通过用第一填充材料填充开口形成通孔基底通孔的方法，并且在第一填充材料上沉积第一绝缘层，第一绝缘层不被沉积在填充材料的侧壁上 所述开口，其中所述第一绝缘层的侧壁在所述开口上形成间隙。 该方法还包括通过使用第二绝缘层密封开口来形成空隙。

公开(公告)号：US12278275B2

公开(公告)日：2025-04-15

申请号：US18093434

申请日：2023-01-05

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Rudolf Berger ,  Helmut Brech ,  Olaf Storbeck ,  Haifeng Sun ,  John Twynam

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/268 ,  H01L23/29 ,  H01L23/31 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778

Abstract: A method includes providing a semiconductor body, forming a thermosensitive element on or within the semiconductor body, forming a structured laser-reflective mask on the upper surface of the semiconductor body that covers the thermosensitive element and includes first and second openings, and performing a laser thermal annealing process that transmits laser energy through the first and second openings and into the semiconductor body, wherein the thermosensitive element comprises a critical temperature at which the thermosensitive element is irreparably damaged, wherein the laser thermal annealing process brings portions of the semiconductor body that are underneath the first and second openings to above the critical temperature, and wherein during the laser thermal annealing process the thermosensitive element remains below the critical temperature.

公开(公告)号：US12230689B2

公开(公告)日：2025-02-18

申请号：US17145507

申请日：2021-01-11

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  John Twynam

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778

Abstract: In an embodiment, a method for fabricating a semiconductor wafer includes: epitaxially growing a III-V semiconductor on a first surface of a foreign wafer having a thickness tw, the first surface being capable of supporting the epitaxial growth of at least one III-V semiconductor layer, the wafer having a second surface opposing the first surface; removing portions of the III-V semiconductor to produce a plurality of mesas including the III-V semiconductor arranged on the first surface of the wafer; applying an insulation layer to regions of the wafer arranged between the mesas; and progressively removing portions of the second surface of the wafer, exposing the insulation layer in regions adjacent the mesas and producing a worked second surface.

公开(公告)号：US20240258382A1

公开(公告)日：2024-08-01

申请号：US18442743

申请日：2024-02-15

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  John Twynam

IPC: H01L29/40 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L21/765 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.

公开(公告)号：US20220254913A1

公开(公告)日：2022-08-11

申请号：US17733009

申请日：2022-04-29

Applicant: Infineon Technologies AG

Inventor： John Twynam ,  Albert Birner ,  Helmut Brech

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/265 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/66

Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.

公开(公告)号：US20210384318A1

公开(公告)日：2021-12-09

申请号：US16894223

申请日：2020-06-05

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Rudolf Berger ,  Helmut Brech ,  Olaf Storbeck ,  Haifeng Sun ,  John Twynam

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/10 ,  H01L29/417 ,  H01L21/265 ,  H01L29/205 ,  H01L23/29 ,  H01L23/31 ,  H01L21/02 ,  H01L29/778 ,  H01L21/268

Abstract: A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.